[J-core] Happy new year.

Rob Landley rob at landley.net
Sat Jan 2 04:21:41 UTC 2021

We're still here, working on stuff. Sorry for the radio silence, there are
actual marketing people who in theory they were going to redo the j-core
website, and in practice have been busy with B2B stuff, so I should take this
over again and start updating the website (with my sad "editing raw html in vi"
skills) and posting updates here.

The xilinx proprietary toolchain continues to be a pain in the neck, but lattice
has made some larger (ecp5) FPGAs you can fit a reasonable SOC in. (The downside
is they're DOG SLOW, like clocking 1/4 the speed of spartan 6.) Still, if
somebody's interested in a port to something like


We can probably get j-core running on that, AND it should work with the fully
open toolchain.

(Speaking of which, I need to redo https://github.com/landley/yogh because
https://github.com/YosysHQ/yosys/commit/a652430c711b made things potentially
more integrated. I also need to look at
and https://github.com/rlee287/ghdl-yosys-plugin/tree/vhdl_backend/src)

In other news, I hate to mention anything that hasn't been released yet but
we've gotten the darn clearances to release J32, and are working to get that up
on github. (It's a branch off of an older SOC version so there's some porting
and disentangling to do, but work on that is actually happening rather than
planned. Yay. Thanks to Jeff Garzik for getting that unstuck.)

We've done a bunch of other things that sadly aren't useful here yet. (For
example, we did a USB 2.0 CDC-ECM ethernet implementation, which has been
working fine since november, but it needs a USB phy chip wired up to the SOC and
we only made 10 instances of that expansion board...

Anyway, just wanted to say we're still at it. Sorry we haven't been very
communicative, but 2020 didn't leave any of us with a lot of spare energy. I'll
try to do better...


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