[J-core] Turtle Board Documentation
w4m4ck at gmail.com
Sat Apr 10 10:56:25 UTC 2021
sorry for jumping in...
> P.S. We sometimes talk about doing a 2.0 design someday with an ICE40 J1 instead
> of Atmel, maybe Artix-7 and DDR3, possibly USB-C and an SDIO wifi chip... dunno
> when Pi 3 form factor stops being useful and we'd need pi 4 to get cases? Except
> what we REALLY need to make is a Lattice ECP5 board that can run J2 (since that
> can use the open GHDL toolchain, although the result's probably like 12mhz
> because ECP5 is _slow_). But again... that doesn't solve the problem that we're
> not set up for retail sales. We're pretty good at designing new boards in house
> and doing a run of a few dozen prototypes, we've already made multiple "hat"
> boards that plug into the 1v1 Turtles for various development projects. And we
> can set up high volume manufacturing to hand off to a B2B hardware partner that
> can deploy a zillion boards into some supply chain. It's the "sell small
> quantities retail" part in between that's... not what we do. And things like
> kickstarter or "amazon fulfillment" turn out not to actually do the bits that
> are missing.
TL;DR i have been looking into giving (after 20yrs back @univ) fpga a second
"chance" because of all the awesome open source achievements regarding
yosys, nextpnr, ghdl, ....
there are a couple ECP5 boards out there which could be used as "base" for
a sh2/j2/j1 core:
i bought a lambdaconcept ecpix-5 with an ecp5 45F couple days ago.
99€. (also, almost
none of the projects mentioned above have boards ready to buy ...)
besides the j* core there is a 20yrs old sh2 verilog implementation available at
- https://www.patreon.com/srg320 <- this guy is working on a sh2 fpga
in order to be able to simulate a sega saturn system in its entirety
using the MiSTer-FPGA
(basically Cyclone V in form of
de10 nano plus sandwich pcb(s)) requires intel quartus which was a
show stopper for me.
that guy doesn't care about j-core. he implements from scratch
according to a twitter post.
(understandable, because for emulation the result needs to be cycle
accurate wrt orig sh2).
actually i'm more kind of a low-level c++ with inline asm hacker than
however, the sh2 is an awesome very compact isa. much more accessible
than riscv. i
think because i'm used to x86 2-address code more then 3-address code
of arm or risc*.
so i tried to get a softcore working on the ecp5. on the road picking
up a "design" i got
kind of overwhelmed by the various different board variants software and $stuff.
what would be an awesome "mini" project: porting the fpga fantasy
console to sh2:
first to use an sh2 core instead of the picorv32 / vexriscv. then get
it running on my ecpix
(which is not compatible to the ulx3s which is supported out of the box).
regarding your speed concerns on an ecp5: the microwatt powerpc
including fpu synthesizes successfully
for an 85F using like 80-90% resources at 40Mhz. (via
ghdl/yosys/nextpnr). my 45F
variant is too small for this.
during the synthetization trial and errors i realized that the
j1-core-ghdl uses twice as much
resources on the fpga as the full icestation-32 soc. (well, j1 core
took like 15-20% resources afair).
i expected the opposite because of (almost) 16bit "only" opcodes.
rounding up: i hope i can get the j1 or aquarius running on my ecp5
board. i don't care about
linux i want bare metal for starters. unfortunately, my vhdl/verilog
skillz are basically non-existent...
it would be awesome if the j-core team could partner up having a low
cost "easy" to use fully
open source solution available. i understand that low volume
productions are not your business,
yet it seems that there is an enormous momentum building up.
all the best, al3x
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