[J-core] Microcontroller variant of J-Core?

[Andrew Pullin]

Hi folks,

I was turned onto J-Core after I saw it mentioned in Twitter. The 
project seems interesting.

Is there currently, or could there potentially be, a configuration of 
J-Core targeted to implementing microcontroller class devices?
No MMU, no linux, just "bare metal" and libc.

I did see some other mailing lists posts mentioning the lack of an 
SRAM/SDRAM controller.
Hooking that up to the BRAM generators/macros in modern FPGAs might be 
an interesting solution.
(but being an FPGA novice, this is beyond my skill level at the moment)
Or in the case of the ice40K, just connect directly into the moderately 
sized dedicated SRAM.

The curiosity comes from what I perceive as a trend in the FPGA/IC 
sector at the moment:
Seeing that ARM is making their M0/M1 cores available for free trial 
suggests that they feel the pressure of RISC-V.
And there is always Microblaze in certain toolchains, but that is a 
licensed IP product married to a specific ecosystem.

In particular, I am interested in a system that blurs lines between 
firmware and hardware definition, where a minimal core would drive a set 
of application-specific peripherals, potentially dramatically reducing 
the complexity of the firmware.
And application-specific instructions would be the ultimate extension 
thereof.
A free and in-the-clear minimal 32b MCU core with gcc/llvm/libc support 
could be an enabler for that goal.

Do the authors & experts here think that J-Core might be a candidate for 
that application?

And is there a more current distribution or repository than the 
"Download" link on the website? The latest there appears to be from 2016.

Thanks,
Andrew Pullin