[J-core] USB 2.0 in turtle

Tim 'mithro' Ansell mithro at mithis.com
Mon Jun 22 07:57:32 UTC 2020

On Sun, Jun 21, 2020, 7:59 PM Rob Landley <rob at landley.net> wrote:

> Sorry for the radio silence, we got buried in $DAYJOB work again. But
> here's an
> issue I've been meaning to document:
> Although the USB 2.0 spec maxes out at 60 megabytes/second (480
> megabits/second), both rounds of turtle board prototypes we did only have
> 1.1 wired up to the USB switch chip that goes to the 4 ports. This doesn't
> cause
> a compatibility issue (the switch chip upconverts the USB 1.1 signal to
> USB 2.0
> as switches do), but the max bandwidth to the j-core SOC through this
> connection
> is only 1.5 megabytes/second (12 megabits).
> The reason for that limitation is the spartan FPGAs can't actually
> generate a
> USB 2.0 signal because it can't clock one pin fast enough. It can do 12mhz
> serial output fine, but 480 mhz straight from an FPGA pin ain't happening.

Which Spartan are you using?

On the sending side, any IO pins on the Spartan 3 can go up to 750mbit/sec
and the Spartan 6 can do up to 1250mbit/sec. Spartan 7 can do 1500mbit/sec
on every pin with a tiny bit of overclocking.

The receiving side is a little bit harder unless you have a good reference
clock. On the Spartan series it is reasonably hard to get the 4x
oversampling of a 480mbit/sec required to do proper clock recovery
otherwise but there are some tricks using the IO delay phasing in a
differential pair.

It is likely we will explore some of this in the Luna stack (
https://github.com/greatscottgadgets/luna) in the future.

Tim 'mithro' Ansell
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