[J-core] Reduce FPGA foot print of multiple softcores on one FPGA by sharing multiplier, barrelshifter, divider or FPU between them

Joh-Tob Sch├Ąg johtobsch at gmail.com
Tue Oct 15 12:01:34 UTC 2019


i came across the attached presentation. Their simulations showed that
sharing a single multiplier, barrelshifter, divider or FPU between two
soft-cores has a non significant impact on performance in many work
loads but can reduce die space.
In their "simulations" they did not actually include the multiplexing
logic. Neither the less i found the idea promising.
This leads to many options what components are shared or not. They
assumed that each component adds a fixed value and used Knapsack to
optimize this.
Is that something worth looking into for J-Core?
Are there some FPGAs which barely do not fit 2 cores where this might
be interesting?

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