[J-core] Threading idea.

[Joh-Tob Schäg]

On Thu, 17 Oct 2019 at 22:14, Rob Landley <rob at landley.net> wrote:
>
> Jeff and I have discussed adding thread support with register banks to j-core,
> where "which thread I'm running" is just a couple unused bits out of the status
> register, and each time you change those bits the next instruction that gets run
> is from a different set of registers including a different PC. :)

This implementation seems to differ from my understanding of the SH3's
register banks. They had a single flag which switched out the lowest 8
general purpose registers for another set of 8 registers. The
non-active 8 general purpose register were still available over copy
from register-to-register instructions. Although there might be some
interaction with the cpu-mode bit.

Is that on purpose?
I feel like swapping out 32 register is a big latency spike, which is
why the register banks were introduced in the first place (fast
interrupt processing without touching the stack).
Does it cause much latency in the current implementation?
Is it going to cause problems in ASIC?