[J-core] We're not making ELC Europe.

BGB cr88192 at gmail.com
Thu Oct 3 07:26:47 EDT 2019

On 10/3/2019 3:50 AM, wjones at wdj-consulting.com wrote:
>> LX45 is large enough for J32 (aka J4) MMU SMP, and probably UP J64.
> Will the LX25 be large enough for J4 single processor? Not too worried 
> about SMP, but I would like to run a CPU w/ an MMU on this board.

Looking it up, it should be possible.
In many areas, stats for the XC6SLX25 are comparable to those of the 
XC7S25 (though, the latter has fewer LUTs, but more DSP's and BRAM; both 
use LUT6's).

Though, unrelated, I have fit my own cores (as a 64-bit ISA with 32 
GPRs, also with MMU and FPU, and some peripheral hardware), onto an XC7S25.

Main concern is that SH4 wants a 64-entry fully associative TLB, which 
is rather expensive.
A cheaper alternative is a 64x4 (4-way associative) TLB, which despite 
conceptually being ~ 4x larger (256 entries total), ends up using less 
resources. Was never fully confirmed, but Linux shouldn't notice all 
that much if it is different.

Another slightly problematic area is that the way SH4 does its FPU 
registers and state, which adds some cost.

Some cost-saving options are to only use a single mode (say, double 
precision), reuse GPRs for FPU (only really viable with 64b GPRs), and 
omit hardware support for "expensive" features (FDIV, FSQRT, denormals, 
alternate rounding modes, ...). This makes the FPU no longer IEE-754 
conformant, but does notably reduce cost without much visible impact on 
application code.

Sadly, there isn't really a good way to change any of this for SH4, so 
its FPU would end up naturally being more expensive. One would also end 
up with either needing to shim format conversion in with register 
fetch/writeback (adds latency), or to effectively have both a single and 
double precision FPU running in parallel (more expensive), more so as 
one needs a bunch of extra state-machine logic or similar to deal with 
FDIV and FSQRT (basically, one reroutes the "plumbing" for the FADD and 
FMUL units through some internal registers to perform Newton-Raphson via 
a state-machine).

But, still, an SH4 should still fit I would think...

> -----Original Message----- From: D. Jeff Dionne
> Sent: Wednesday, October 02, 2019 5:38 PM
> To: Joh-Tob Schäg
> Cc: j-core at lists.j-core.org
> Subject: Re: [J-core] We're not making ELC Europe.
> On Oct 2, 2019, at 17:29, Joh-Tob Schäg <johtobsch at gmail.com> wrote:
>> Thank you for letting us know.
> Hi Joh-Tob, quickly:
>> I could find any information about specs of the turtle board on the
>> website (http://j-core.org/turtle/). Since you are moving into
>> production the specs should well known.
> Yes.  This is 1v1, basically the same as the previous prototypes, with 
> some component changes.
>> Could you enlighten us about what FPGA made it and the other specs of 
>> the board.
> The device choice is XC6SLX25 or XC6SLX45, both in a IIRC 326 PBGA, 
> with LP-DDR memory
>> What does that FPGA choice means for the turtles viability as a dev
>> board in the future? In the IRC i saw the question whether the board
>> will be big enough for a J4 or a J64.
> LX45 is large enough for J32 (aka J4) MMU SMP, and probably UP J64.
>> Additionally are you looking for other conferences to present at?
> Yes.  We need to do that.  We’ll have physical units people can walk 
> away with at any conferences we go to.
>> There are a few more events this year:
>> http://www.linux-magazine.com/Resources/Event-Calendar
>> Including at the end this year (27.-30. December) there is the 36.
>> Chaos Communication Congress (36C3) in Leipzig, Germany. They are
>> known to be very capable with recording talks but i guess getting a
>> spot now could be though.
> We’ll take a look!
> Cheers,
> J.
>> On Wed, 2 Oct 2019 at 21:33, Rob Landley <rob at landley.net> wrote:
>>> Alas, the turtle board components got held up in customs for a week, 
>>> so the
>>> completed boards are expected to leave the factory on the 19th, 
>>> meaning having
>>> boards ready at ELC on the 28th seems unlikely.
>>> So we're probably doing a small crowdsupply campaign without 
>>> announcing it at a
>>> conference, just to get the boards available, and then try to have a 
>>> HAT board
>>> (probably the GPS hat) ready to launch at a conference early next 
>>> year..
>>> Rob
>>> _______________________________________________
>>> J-core mailing list
>>> J-core at lists.j-core.org
>>> http://lists.j-core.org/mailman/listinfo/j-core
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> William D. Jones
> wjones at wdj-consulting.com
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