[J-core] Reduce FPGA foot print of multiple softcores on one FPGA by sharing multiplier, barrelshifter, divider or FPU between them

D. Jeff Dionne Jeff at SE-Instruments.com
Fri Dec 27 16:28:57 UTC 2019

Resource sharing is a very useful approach.

The multiplier is basically not a win, basically for the reasons you imply: the multiplexing is non trivial.  J2 achilles heal is the muxing in the datapath already.  OTOH, the multipliers are hard macros in modern fpgas.

The J2 barrel shifter is optimized for 4 input lut architectures, in the current implementation.  It’s pretty big, and that might be a good candidate.

But making a generic coprocessor interface multiplexor seems like it might be a good idea.  We had intended the FPU to be one instance per 2 cores anyway...


> On Oct 15, 2019, at 08:00, Joh-Tob Schäg <johtobsch at gmail.com> wrote:
> Hello,
> i came across the attached presentation. Their simulations showed that
> sharing a single multiplier, barrelshifter, divider or FPU between two
> soft-cores has a non significant impact on performance in many work
> loads but can reduce die space.
> In their "simulations" they did not actually include the multiplexing
> logic. Neither the less i found the idea promising.
> This leads to many options what components are shared or not. They
> assumed that each component adds a fixed value and used Knapsack to
> optimize this.
> Is that something worth looking into for J-Core?
> Are there some FPGAs which barely do not fit 2 cores where this might
> be interesting?
> Thanks
> <iccad06_conjoin.ppt>
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