[J-core] Turtle FPGA

[D. Jeff Dionne]

Hi Cedric,

Yes, we agree with this.   Our customer facing work has moved to Kintex 7 quite a while back.  The turtle project has not stalled completely, but resourcing has been hard... in the mean time, fpga vendors and tools march foreword.

The only sticking point for a J-Core build is Artix 7 requires Vivado, and our build system doesn't know how to drive those tools.  K7 can still be targeted by the ISE tools, so that was easy.  We are told by the Xilinx tools group that Vivado will produce better results (specifically, the placer in Vivado is supposed to do a much better job).

We don't think that driving Vivado tools with a Makefile based build system is hard... we just haven't had time to try it.   Of course, we are all for yosys targeting fpga families and processes we target, that is ideal.   The sticking point for yosys remains vhdl front end support, and that has proven to be a harder problem than many suspected.   I remain convinced that a path there is NVC -> intermediate netlist -> yosys.

Cheers,
J

> On Jan 5, 2018, at 14:43, Cedric BAIL <cedric.bail at free.fr> wrote:
> 
> Hello,
> 
> I discovered today the attempt to have the Artix 7 XC7A50T FGG484
> bitstream reverse engineered like it has been done with the iCE40. The
> project is at : https://symbiflow.github.io/ .
> 
> This Artix 7 is in the ballpark of price and characteristic of the
> LX45 that was envisionned at some point for the higher end version of
> the turtle. I don't really know what are the drawback of that familly
> compared to the Spartan 6 and why the Spartan 6 were preferred, but if
> the development of the Turtle board still allow for it, looking at
> switching to this XC7A50T would make a potentially very nice platform.
> 
> What are your thinking on this ?
> -- 
> Cedric BAIL
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