[J-core] [RFC] SIMD extention for J-Core

[Ken Phillis Jr]

Information on the SH-3 Is not exactly sparse, This processor has 3
main versions:
SH-3: The Feature added in this is MMU Instructions, and these are
generally in the System Control Instructions
SH-3E: the SH-3 Instructions with 32-bit Floating Point Instructions
and registers added.
SH3-DSP Core: SH-3 Instructions with Arithmetic DSP Instructions
added. In general these are mostly for Integer and fixed point math.

Also, To see a comparison of the SH1, SH2, SH3, and SH4 lines of
chips, you can find the instruction set summary for these at:
HTML: http://www.shared-ptr.com/sh_insns.html
Github: https://github.com/shared-ptr/sh_insns


Also, You can find the Programmers manual for the SH3 by searching the
Renesas Website for the SH7705 chip, and looking for the following
Document:
SH-3/SH-3E/SH3-DSP Software Manual