[J-core] Fwd: ISA manual for SH-2

Francisco Javier Bizcocho Antúnez volkovdablo at gmail.com
Sun May 28 13:16:57 EDT 2017

Thanks for the explanation Jeff, and yes indeed it requires a special jtag
probe and comercial IDE. In my case I'm using CodeScape and their Classic
DASH to do all of this. The IDE also provides the debug stub, that will be
injected in RAM in the address that I previously specify. The only problem
that I have is that, apparently there is a 'secret' register called SDSR,
that contains the ID of the processor, (or at least some kind of ID) that
the probe uses to carry on with the debugging session. The funny bit is
that this register must be somehow initialized from the boot rom, or the
probe just refuses to connect to the CPU.
This register can be modified from the CPU I believe. And what I'm doing is
basically running a program that goes through all the Physical address
space, looking for the value 0x12345678 (which is the current value of

On Sun, 28 May 2017 at 12:51, D. Jeff Dionne <Jeff at se-instruments.com>

> The JTAG debug on SuperH is implemented with (essentially) normal ISA
> instructions in a protected on chip 'ASE' memory block.  It is a debug stub
> speaking a proprietary protocol over JTAG, with hardware support on chip so
> that it can always trap into the stub.  This is flexible, but takes up a
> large amount of unproductive die area (in actual use).  A special jtag pod
> (E10A) is used, and the software requires Windows to run HUE (proprietary
> IDE).
> J-Core takes a different approach.  The scan chain has a few bits
> (basically, IIRC, 56 bits total) to stop/step the CPU, insert an
> instruction into the fetch stage, and scan out the writeback bus.  total
> overhead is something like around 60-100 flops for the scan chain and
> capture regs, and a few dozen mux cells (assuming you had a TAP controller
> anyway).
> So, unfortunately, we don't have any way to help with the (very different)
> SH implementation...
> Cheers,
> J.
> On May 28, 2017, at 04:59, <volkovdablo at gmail.com> <volkovdablo at gmail.com>
> wrote:
> Btw, does anybody know anything about the SH4 debug stub that is necessary
> in the ROM to make the JTAG subsystem to work?.
> I’m trying to hook a JTAG to my Dreamcast. So far everything is installed
> correctly, as the probe can detect the CPU. Unfortunately, the rom does not
> initialize the CPU id correctly, and the probe just says “Target not
> recognized SDSR = 0x12345678”.
> I tried everything to find the location of this “SDSR” register, so I
> could initialize it to something during the boot rom. But there is no
> information whatsoever about this. Even Renesas refuses to answer me.
> Anyone can bring some light to this?
> Thanks in advance,
> Javier.
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