[J-core] Sorry for the radio silence.

[Rob Landley]

On 05/14/2017 06:12 PM, BGB wrote:
> yeah, looking into it, it apparently is pretty variable (depends on the
> type of FPGA and the vendor).

Think of each FPGA vendor as a different architecture target
(arm/mips/sh/x86/cris/powerpc/sparc) different toolchains target. And
each ASIC fab is _also_ a different target. (Moving from 150 to 45
nanometers at the same company, 2 different 45 nanometer fabs from
different companies... all different targets with wildly different
optimization.)

In theory the tools should handle most of this for you. In practice,
it's a bunch of different proprietary toolchains, often outright buggy.
You need all the tests in the world...

> a lot of them use SRAM (apparently the wiring done mostly with flip-flops).
> others use FGMOS (like used in Flash), where basically the residual
> charge held in a MOSFET is used to control whether a connection is
> open/closed (just it requires driving an elevated voltage to change the
> state of the MOSFET).

More patents should expire and advance the FPGA state of the art before
too long. My understanding is Lattice is least proprietary, but also
fairly trailing edge in terms of technology (which hits _us_ in terms of
capacity, the amount of FPGA capacity to emulate an entire processor
simply wasn't a _thing_ 15 years ago, then became available only at the
ultra high end, and is finally reasonably priced but only from certain
vendors and with proprietary tools...)

There's a fun talk an AMD guy gave a while back about how they can't
simulate their chip design in even the highest-end FPGAs because it's
just way too big:

  https://www.youtube.com/watch?v=eDmv0sDB1Ak&t=52m0s

Meanwhile, our stuff fits in the cheap low-end FPGAs. :)

Rob