[J-core] Sorry for the radio silence.
rob at landley.net
Thu May 11 12:34:18 EDT 2017
On 05/10/2017 08:46 AM, Kieran Bingham wrote:
> What SoC are you using for the Turtle?
We aren't. The brain of the thing is a Xilinx Spartan 6 FPGA. There is
no SOC unless you load a bitstream into that FPGA.
There is an 8 bit atmel microcontroller that loads the FPGA at from spi
flash at power-on, and then switches itself off once the FPGA starts
running the bitstream, but it's a brainless little thing running from
something like 8k of its own flash. (The other thing it can do is run a
little program to reflash the spi from usb if you flip the flash/run
switch to flash position; that way the board's a lot harder to brick.)
> Has the boat set sail already?
The FPGA in turtle is not a peripheral bolted to the "real" processor,
no. All the I/O devices on turtle are routed to the FPGA pins, not to an
existing ARM SOC ASIC. (Unless you count the atmel, which can talk to
the usb serial and the mmc bus to load/flash the bitstream to spi flash.
I'm not sure how martin wired that up because it doesn't come up when
the board is running.)
Sorry, I'm going "didn't I just write up a lot post about this in the
context of somebody asking hardware security questions?" But that was on
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