[J-core] Jcore mailing list and tutrle board

D. Jeff Dionne Jeff at SE-Instruments.co.jp
Thu Jul 6 09:11:22 EDT 2017

On Jul 6, 2017, at 5:58, Rob Landley <rob at landley.net> wrote:


Pls see inline.

> On 07/04/2017 02:30 PM, David Summers wrote:
>> On 04/07/17 09:35, Rob Landley wrote:
>>> On 07/03/2017 02:41 PM, David Summers wrote:
>>>> Hi Rob,
> ...
>>>> Anyway, you probably know the answer to what I was planning to ask
>>>> anyway. Why on the turtle boards did you fix on the Spartan FPGA? The
>>>> newer Artix is similar price and newer, e.g.:

The highest volume product Xilinx ship right now is still S6 in the low cost area, not Artix (I have it on good authority).

We have a bunch of products using S6 on the commercial side, we don't want A7 right now.

Once we make a change of tools from ISE to Vivado, we can make a compatible upgrade to either A7 or S7.

>>>> https://shop.trenz-electronic.de/en/TE0725-03-100-2C-FPGA-Module-with-Xilinx-Artix-7-XC7A100T-2CSG324C-2-x-50-Pin-with-2.54-mm-pitch
>>>> a 100k gate FPGA for just over a $100.

And that is another reason why.  $100 is another class of product.  Turtle design goals had a BoM cost of about $50.

>>> This is really a Jeff question, but my understanding is that's only true
>>> in higher volumes. Spartan 6 is available cheap in lower volumes.
>> I'll ask Jeff when I sign up ;)
>> But yes, you answer would make sense, Spartan 6  is end of line - so

No, that is false.  S6 is the current high volume product.

>> Xilinx may well be happing moving just what they have left.

No, most of their customers are still using it.  If they tell you otherwise, they are telling a fib (we know the product line people).

> Last I heard they're still making them, they're cheap, they work, and
> they're what we did the majority of testing on when designing the chip.
> (We've recently moved some stuff to Kintex 7, but that's way more
> expensive.)
>> I expect the line to be dropped soon.

No, that won't happen, it would obsolete their customer designs, which is bad for business.  Most real customers are stubbornly staying put.
>>>> Rather than the usb to write the bitstream did you think of using jtag?

That's for engineers, not experimenters / makers.  If you want to do that, you can connect a JTAG pod to the Turtle.  The goal is zero external tools (which is also the goal on our commercial side).

>>>> E.g. adding FTDI FT232H chip, you could have attached to the jtag pins,

Completely goes against the point of all open hardware.  The AVR that is on the Turtle will be replaced by an ICE40 at some point.  No proprietary processors or interfaces anywhere we can help it.

The point isn't to make another FPGA board, you can buy lots of those.  This is an open Raspberry PI board, where you can change everything.  Different goals.

> Last I tried using OpenOCD 
> *shrug* Maybe it's improved since then...

All those tools are horrible.  The reason is people get them to work for their needs, and once the project is complete walk away.  There are no really serious JTAG tools in the opensource which are clean, extensible and not tied to a specific set of tasks.

>>> C) Requiring openocd setup as a hard prerequisite would probably
>>> eliminate about 2/3 of our userbase.

Yes, this is the point.

>> In work we always buy
>> what FPGA say you use, which again is $$$$. open jtag is something new,
>> so little software out there -

Which is why this looks very different.  We don't use anything the vendor requires, because that locks in the vendor.  The synthesis tools are wrapped in Makefiles, and you can replace them with another toolchain.  This is not a Xilinx, S6 (or A7) board.  It's a board that happens to use an S6 to carry the J-Core SoC.  Some of our customers use K7, it will be available on a TSMC process soon... Nothing we can't replace can be used.

>> and not much call as people doing FPGA unless professionals (where  time is $$, so $$$$ for software is a win).

Which is why this isn't an FPGA board, it's a board that has an SoC in FPGA.

> We're trying to bring FPGA stuff to hobbyists. An atmel boot processor
> that flashes the thing from a file on the sd card so you don't _have_ to
> master a jtag before you can update your FPGA image was considered a win.

> Searching my back email for openocd didn't bring up the thing that's not
> openocd, though. Mostly it's threads about debugging GDB integration for
> superh...

The SH JTAG is an example of why we don't do things the vendor way.  The original implementation might be great (some of our engineers designed it originally, after all) but it doesn't matter... the only pod that works is something like $500, and the software is windows only.  Useless to most people out of the gate, and useless to everyone 10years on.


> Rob
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