[J-core] Adding SH2/SH4 support to LiteX using J-Core?

Tim Ansell mithro at mithis.com
Mon Feb 6 12:14:31 EST 2017

Hi J-Core developers!

I'm the creator of HDMI2USB.tv, a system which uses FPGA hardware to create
FOSS systems for capturing user groups and conferences. To do that we use a
Python based "System on Chip" solution called LiteX[1] (based on
Migen+MiSoC[2]). I actually gave a talk on why we do this at Linux.conf.au
2017 recent[3] that Rob Landley was also speaking at.

 [1]: https://github.com/enjoy-digital/litex
 [2]: https://m-labs.hk/gateware.html
 [3]: https://www.youtube.com/watch?v=MkVX_mh5dOU - Using Python for
creating hardware to record FOSS conferences!

One of the nice things about LiteX is that it supports multiple different
soft CPU implementations by just changing one argument. Currently we have
support for the lm32, mor1k & picorv32[4]. However, at the moment we don't
really have an architecture which has both good upstream GCC (and related)
and good upstream Linux support.

 [4]: https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu

Hence, I'm really interested in adding "J-Core" / sh2+sh4 support to that
list and wanted advice about the best way to approach this problem. As we
already have our own set of peripherals (UART, DDR controller, Ethernet,
etc) we just want to use the CPU core rather than your full SoC. Do you
have any advice on the best way to do this? What would be the best way to
extract "just the CPU"?

Normally we would use something like Verilator or iVerilog to get the
basics working (CPU executing instructions and interrupts) in simulation,
but as J-Core is VHDL there doesn't seem a good FOSS option for doing
things that way (although I guess we could try rqou's co-simulation

 [5]: https://github.com/rqou/myhdl-vhdl-verilog-test

Most interested developers already have a MimasV2 platform and we have
gotten many of the peripherals working with LiteX already.

Thanks for your help!

Tim 'mithro' Ansell
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