fsukalia at gmail.com
Sat Dec 2 11:57:09 EST 2017
I'm curious about the memory management unit in j2, as it is needed to port
Debian to j-core. The last I read on this mailing list was that the design
of the MMU will be discussed during a meeting in Japan.
Are there any new information that can be shared with the community? Will
it have a soft-mmu, like MIPS and LM32 have, or a hard-mmu like in x86?
Also, will the design be compatible to the MMU in SH-4?
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