[J-core] newbie

Rob Landley rob at landley.net
Thu Aug 10 19:11:49 EDT 2017

On 08/09/2017 04:55 AM, D. Jeff Dionne wrote:
> On Aug 9, 2017, at 08:29, emanuel stiebler <emu at e-bbes.com> wrote:
>> Hi all,
>> watched the video on yutube, from rob & jeff on the embedded linux
>> conference, and thought it is pretty exciting. But, being new to
>> j-core have some questions, and couldn't find the answers easily in
>> the archives ...
> Thanks.  We should put up some FAQs...

I have a bunch of website stuff queued up for when we manage to dig back
down to this...

>> a.) are the source now in GIT, somewhere on github?
> We have not done a release in a while.  Not because we stopped,
> rather the opposite (customer deliverables).

Sigh, you think this project's gotten starved for cycles, you should see
toybox... :P

We don't talk about it much here because we're keeping intentional
distance between the projects, but it's no secret most of the engineers
behind j-core work for https://se-instruments.com. (We're making sensor
systems to allow renewable energy to displace fossil fuels in utility
grids. At our last big conference the banner said "fault resolution to 3
meters". Except in Japanese, because it was "Smart Energy Week" at
"Tokyo Big Site".)

For context why this is such an exciting area to be in right now, here's
a stanford professor named Tony Seba (no relation to us, never met him,
he's just a business-side domain expert in this space) teaching a class
in 2013, then giving a book talk last year, then having his book talk
analyzed by a mutual fund in india earlier this year:


The j-core project is a separate fully open source entity, but there's
some serious resource contention going on right now staffing-wise. Sorry
about that.

>> c.) Anybody is working on interfacing the memory to AXI? I know and
>> understand, that it isn't free, but it can be used by both of the big
>> guys (Altera and Xilinx) and would open the j-core to the newer
>> FPGAs.
> IP rights issues are the main reason we choose to do simple, straight
> forward bus structures.   AXI is interesting, but making sure there
> are no IP problems is a task we've not undertaken.  AMBA bridge is
> also interesting, and there is precedent that it likely has no
> practical problems (LEON and GR Lib) but we've not investigated that
> either.

Also, we did our own DRAM controller even though there's one in the FPGA
because we want to make a fully open-source ASIC. Once the design was
proven in FPGAs, porting it to more FPGAs was lower priority than first
silicon. :)


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