[J-core] [musl] Re: Aligned copies and cacheline conflicts?

[D. Jeff Dionne]

On Sep 17, 2016, at 17:08, BGB <cr88192 at gmail.com> wrote:
> 
> I am left wondering what prevents using a hash in the cache lookup, where presumably a simplistic (presumably XOR based, 1) hash isn't that hard to pull off in VHDL? granted, I don't really know the specifics here.

Cache lookup and fill are fast path operations (no waiting).  Hit shall not cause a CPU stall, and fill shall not incur any more cycles than necessary before the CPU gets the data.  Hash is hugely expensive.  Therefore, N way cache, where N is 1 to about 4 is the order of the day...  Where N>1 requires least recently used logic, etc and we have not implemented that.  Direct mapping gives you by far the largest boost.

J.