[J-core] Aligned copies and cacheline conflicts?

[Rob Landley]

There was a discussion at one point about how reading from and writing
to an alised cache line (anything at an 8k offset) would cause horrible
performance (the write cacheline evicting the read cacheline and vice
versa), how this was a more common problem than 1 in 256 because things
are often page aligned, and how a workaround was to have memcpy read
data into 8 registers and then write it out again from those 8 registers
to avoid the ping-ping.

Question: did that memcpy change actually go into musl and the kernel?
(Seems like both would need it...) If so, what do I have to make sure
I've pulled to get them?

Rob