[J-core] qemu updates / roadmap
Christopher Friedt
chrisfriedt at gmail.com
Wed May 18 12:02:28 EDT 2016
OOoo - interesting. The _testmov subroutine is failing because of bits
in the SH4 SR that are not in the SH2 :-) Simple solution!!
On Wed, May 18, 2016 at 8:42 AM, Christopher Friedt
<chrisfriedt at gmail.com> wrote:
> The next test that is failing is _testmov. The jmp at the bottom is to
> _fail. But we're passing _testbra, which is good, at least ;-)
>
> ┌──Register group: general─────────────────────────────────────────────────────┐
> │r0 0x3f3 1011 │
> │r1 0x1234567 19088743 │
> │r2 0x89abcdef -1985229329 │
> │r3 0x700080f3 1879081203 │
> │r4 0x1234567 19088743 │
> │r5 0x89abcdef -1985229329 │
> │r6 0xffffffff -1 │
> │r7 0xffffffab -85 │
> │r8 0x12 18 │
> │r9 0x0 0 │
> │r10 0x0 0 │
> ┌───────────────────────────────────────────────────────────────────────────┐
> │0x3e7c <_testgo> mov #-1,r0 │
> │0x3e7e <_testgo+2> mov.l 0x4170 <_p01234567>,r1 ! 0x1234567 │
> │0x3e80 <_testgo+4> mov.l 0x4174 <_p89abcdef>,r2 ! 0x89abcdef │
> │0x3e82 <_testgo+6> ldc r0,sr │
> │0x3e84 <_testgo+8> mov.l 0x4198 <_p000003f3>,r0 ! 0x3f3 <start+31> │
> │0x3e86 <_testgo+10> stc sr,r3 │
> │0x3e88 <_testgo+12> ldc r1,gbr │
> │0x3e8a <_testgo+14> stc gbr,r4 │
> │0x3e8c <_testgo+16> ldc r2,vbr │
> │0x3e8e <_testgo+18> stc vbr,r5 │
> │0x3e90 <_testgo+20> cmp/eq r3,r0 │
> >│0x3e92 <_testgo+22> bt 0x3e98 <_testgo+28> │
> │0x3e94 <_testgo+24> jmp @r13 │
> └───────────────────────────────────────────────────────────────────────────┘
More information about the J-core
mailing list