[J-core] Adding J1 to the roadmap.

Christopher Friedt chrisfriedt at gmail.com
Wed May 18 07:07:39 EDT 2016

I like this idea.

I know on Cortex-M0, the software interrupt (svc / swi), was hosed , and I
felt it was a bit of a mistake for Cortex-M0 to silently ignore. The only
suggestion I have for J1 is to not make that same mistake.

>From musl gitweb it appears that "trapa #imm" is valid for SH*, so I assume
that an analog to the above is not the case.

Would we keep the atomic CAS.L? Atomic instructions are nice to have.. for
a lot of reasons!

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