[J-core] SuperH GDB?

[Rob Landley]

On 05/06/2016 01:06 PM, Christopher Friedt wrote:
> Hi list + Rich,
> 
> Do we have a SuperH GDB that is distributed as part of the toolchain?

Rich already replied to that, but regarding your post about ICE40:

https://plus.google.com/+ChristopherFriedt/posts/Tr4NbfdXMJ3

The one you pointed at is too small, but we found a bigger one with
something like 4000 cells. Jeff Dionne attempted a j-core port to that
this past weekend. You have to do a little violence to the design, but
in theory it looks like the processor is in the ballpark of fitting if
you disable cache and prefetch (not needed on something running from
sram) and also yank the multiplier. (So slightly reduced instruction set
but still well past turing complete, and gcc can emit multiple
instructions to do multiplies with shifts and addition the way it often
does that for division.) Then you might have enough gates left for one
instance of the serial port and glue logic to talk to the ICE40's SRAM
block. (It's tight but should be doable.)

Bonus points: you can use an entirely free toolchain to do it, by gluing
the VHDL parser of Nick Gasson's NVC onto the ICE 40 code generator backend.

The first stage of this was to get NVC to do what ghdl does (which is a
bonus in and of itself because C++ is less bad than ADA as an
implementatino language). The end result was that it bulit something
that didn't work right, and Jeff emailed in a bug report and the
stripped down processor build tarball to Nick, and Nick replied on the
fourth that he'd fixed 2 bugs and hoped to have more time to look at it
over the weekend.

Lemme see if I can get permission to repost his message. (In theory NVM
has its own mailing list, but so far I think this has been in private
email?)

Rob