[J-core] Delay slots 2: Electric Boogaloo (Illegal instructions in delay slots)

[Robert Ou]

What value of PC should be saved on the stack when an illegal
instruction is encountered in each of the following?

a) an unconditional branch
b) a conditional branch that is taken
c) a conditional branch that is not taken

The behavior of J-core WITHOUT my patch seems to be:
a) the address of the branch target
b) the address of the branch target
c) the address of the illegal instruction (the address of the delay slot)

The behavior of J-core WITH my patch seems to be:
a) the address of the illegal instruction + 4
b) the address of the illegal instruction + 4
c) the address of the illegal instruction (the address of the delay slot)

The expectation of the Linux kernel with FPU emulation enabled
(do_illegal_slot_inst when CONFIG_SH_FPU_EMU is defined) seems to be:
a) the address of the branch (the address of the delay slot - 2)
b) the address of the branch (the address of the delay slot - 2)
c) the address of the branch (the address of the delay slot - 2)

The expectation of the Linux kernel on fixing alignment errors
(handle_unaligned_access, not actually used for J2) seems to be
(according to the comment above the code for SH3):
a) the address of the branch (the address of the delay slot - 2)
b) the address of the branch (the address of the delay slot - 2)
c) the address of the illegal instruction (the address of the delay slot)

Which set of behaviors (if any) is correct?

Robert