[J-core] Illegal instruction handling (was: Re: PC-relative loads and delay slots)

[Rich Felker]

On Wed, Jul 20, 2016 at 11:25:14AM -0700, Robert Ou wrote:
> On Jul 20, 2016 9:13 AM, "Rich Felker" <dalias at libc.org> wrote:
> >
> > On Tue, Jul 19, 2016 at 11:40:17PM -0700, Robert Ou wrote:
> > > I just tested illegal instruction handling, and it does "work" with
> > > some caveats:
> > >
> > > a) Illegal instruction checking is very limited as Geoff just explained.
> > >
> > > b) The vector used by illegal instructions is always hardcoded to 0.
> > > This happens on line 78 of decode_core.vhm:
> > > cd := x"0" & system_instr_codes(instr) & x"00";
> > > If you change the x"00" to something else, then all "system operations
> > > that are not external events" (slot illegal, general illegal, and
> > > break) will then use that new vector.
> >
> > Do you mean it's ignoring the exception vector table at VBR and using
> > a fixed address of 0? If so, I think this needs to be fixed in order
> > for the trapping to be usable, but I didn't see anything in your patch
> > that addresses it.
> 
> No, it's using the address stored at VBR+0 always (the reset vector).
> This is also pretty useless, and in my test I just changed it to x"02"
> arbitrarily. Yes, this also needs to be fixed, and I didn't address it
> in my patch. I didn't actually find anything that specifies what
> vector number it is actually supposed to use.

Ah, then that should be easy to fix. As far as I know (though I can't
find them in the official docs), the right VBR slots are:

# define TRAP_RESERVED_INST     4
# define TRAP_ILLEGAL_SLOT_INST 6

I'm pretty sure they need to be distinct traps in order for the
handler code to correctly trap-and-emulate both cases.

Rich