[J-core] Illegal instruction handling (was: Re: PC-relative loads and delay slots)

[Rich Felker]

On Tue, Jul 19, 2016 at 11:40:17PM -0700, Robert Ou wrote:
> I just tested illegal instruction handling, and it does "work" with
> some caveats:
> 
> a) Illegal instruction checking is very limited as Geoff just explained.
> 
> b) The vector used by illegal instructions is always hardcoded to 0.
> This happens on line 78 of decode_core.vhm:
> cd := x"0" & system_instr_codes(instr) & x"00";
> If you change the x"00" to something else, then all "system operations
> that are not external events" (slot illegal, general illegal, and
> break) will then use that new vector.

Do you mean it's ignoring the exception vector table at VBR and using
a fixed address of 0? If so, I think this needs to be fixed in order
for the trapping to be usable, but I didn't see anything in your patch
that addresses it.

Rich