[J-core] What is the correct way to reset the CPU?

[Rob Landley]

On 07/18/2016 10:55 AM, D. Jeff Dionne wrote:
> There is one more problem... The boot code is not 'rom', and would have to have .bss zeroed and .data reinitalized.  This needs to be fixed, with a new linker script and crt0
> 
> Cheers,
> J.

Are you referring to the way the FPGA version repurposes some SRAM to
act like a boot rom, and has circuitry that loads initial values into it
on power on? That circuitry isn't getting called again on reset?

(I thought the ASICs would have actual boot ROM?)

Rob