[J-core] J-core address errors and other questions

[Robert Ou]

Hi,

I am interested in possibly using the J2 core for some of my projects.
I am currently trying to see how difficult it would be to add a simple
base and bounds MPU with a fixed number of regions. However, it is not
entirely clear to me how the exception logic in the core works and how
I can correctly trigger a bus abort. I can see that interrupts, errors
of some kind (address errors?), debug breaks, and resets can be
injected using the event_i and event_o ports. However, looking at the
"Detect Exception Events" logic in decode_core.vhm, it appears to
imply that a) errors can only be triggered on instructions not in a
delay slot and b) errors can only be triggered after completing the
current instruction. Is my understanding correct? More specifically
for b, does it mean that, in the current implementation, it is not
possible to trigger an external event when a bus cycle is not yet
completed (inst_i.ack/db_i.ack has not become 1)?

I am also trying to understand why the microcode operations for
illegal instructions and interrupts are a) the way they are and b)
quite different. From what I understand of the microcode, the handling
of an illegal instruction is essentially:
1. Decrement PC by 2 or 0 so that it points at the next instruction
(isn't decrementing by 0 pointless?)
2. Store SR at *(--R15)
3. Store PC at *(--R15)
4. Read from VBR+off
5. Do nothing (wait for reading to happen?)
6. Update PC with value read
7. Make IF fetch from this new address
8. Poke instruction dispatch? (I don't quite know what this does as I
don't have a complete picture of all the pipeline control signals yet)
Meanwhile, the handling of an interrupt seems to be:
1. Decrement PC by 2 so that it points at the next instruction. Also
acknowledge interrupt and remember the current interrupt level
(where?)
2. Transfer R15 to TEMP0 (What does FC in the ALU X do? Why is the
TEMP0 necessary? Why couldn't R15 be used directly? Why doesn't
illegal instruction require TEMP0?)
3. Store SR at *(--TEMP0)
4. Store PC at *(--TEMP0)
5. Read from VBR+off
6. Decrement R15 by 4 and also change interrupt mask level. (Meanwhile
waits for reading to happen?)
7. Update PC with value read
8. Decrements R15 by 4 again (couldn't step 6 just decrement by 8?),
and also makes IF fetch from the new address.
9. Does nothing?? (Why doesn't it poke instruction dispatch like an
illegal instruction?)
Is this approximately correct? Could someone clarify the points I am
unclear about?

As an unrelated question, I would also like to know what happens when
the CPU attempts an unaligned read/write or a jump to an unaligned
address. From what I can see, the CPU just seems to assume that this
doesn't happen and essentially would end up incorrectly rotating
various bits around when an unaligned access is attempted. Is this
accurate or did I miss a check for alignment somewhere?

Robert