[J-core] J-core ASIC, What tools should be used?
daniel.viksporre at gmail.com
Sat Aug 20 03:27:12 EDT 2016
If you would like to look into making a custom CMOS design for j-core,
is there any ideas on what tool-chain to use for that?
Maybe the design can be sized so that four layers can fit on a blank,
for a multilayer mask(MLM). That is 4 layers on one mask, instead of
paying for 4 masks.
But what type of process would it be preferable to design for? And
what design rules should be used (do fabs provide that information
without you sining a non disclosure agreement)?
// Daniel V.
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