[J-core] Linux on J1?

Rich Felker dalias at libc.org
Tue Aug 2 16:06:41 EDT 2016


On Tue, Aug 02, 2016 at 02:54:36PM -0500, Rob Landley wrote:
> > If we wanted GCC to support an ISA-subset J1
> > directly, either FDPIC support should be added to the existing SH-1
> > target (not too difficult but upstream would end up with extra mess to
> > maintain) or J1 could be added as a new ISA level (complexity burden).
> 
> Presumably we'd want a "gcc -mj1" target, but we'd want that even if we
> weren't thinking about trying to run Linux on it.

Yes, we'd probably need that for cas.l support anyway, in which case
we'd be incurring some of this complexity cost (enlarging the graph of
ISA levels) in the tools already.

> > If microcoding is practical, I think that makes a lot more sense. It
> > should both perform better and avoid big software dependencies.
> > 
> >> 4) Tweak gcc/binutils to add a target to produce the right instructions.
> >>
> >> 5) Tweak the kernel assembly.
> >>
> >> 6) Boot Linux on a Numato board with J1.
> >>
> >> Now here's the really funky question: If we just use prefetch instead of
> >> icache/dcache, could we SMP J1 on Numato? (And/or fit in one instance of
> >> the DSP?)
> > 
> > Disabling dcache is a huge hit to performance.
> 
> I also forgot that CMPXCHG and our memory barrier stuff is currently
> implemented as cache tricks. Right now we CAN'T do SMP without the cache.

I'm not sure where you got that. It works fine with dcache off, and
IIRC it even works on sram too (though not on mmio registers, of
course).

> > It might be more
> > practical to do a shared-dcache implementation for SMP, where both
> > cores are accessing the same cache (even if subject to stalls when
> > both access it at the same time) that would allow all the snooping
> > logic (and half of the cache memory size) to be omitted.
> 
> I'm not sure what actually saves resources in the FPGA, the SRAM banks
> are there either way. (Wiring them up takes the kind of cells we tend to
> run out of...)

I would think an LX25 or LX45 has more sram space than an LX9 or
ICE40, but that's just a guess; maybe they all have a plenty.

Rich


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