[J-core] What's involved with putting serial ports on GPIO pins?

Geoff Salmon gsalmon at se-instruments.com
Fri Apr 29 22:31:27 EDT 2016

On 16-04-29 12:37 PM, Geoff Salmon wrote:
> On 16-04-29 12:56 AM, Rob Landley wrote:
>> Could we document how to do that? It seems like a fun "get your hands
>> dirty" electrical experiment that's less likely to fry the board than
>> some. :)
> I can describe how to connect the uartlite to the gpio pins within the
> bitstream. I don't know what needs to be physically connected to the
> gpio pins. Something like this
> http://store.digilentinc.com/pmodusbuart-usb-to-uart-interface/ might work.

I looked closer at the Mimas v2 docs and those headers do look pmod 
compatible, the gnd and 3v3 are in the right place, so I think that 
Digilent usb-uart board will work. We have used that same usb-uart board 
with a different one of our boards and it worked. That was using a 
uart16550 with the RTS and CTS pins also connected. As we're using the 
uartlite in the mimas_v2, we might need to tie the RTS low (I think it's 
active-low?) but it may not matter.

If anyone has a usb-uart board like this and wants to try it, let us know.

> We don't yet have documentation for what soc_gen expects to see in the
> edn file, but I'll describe enough below to change where the uartlite's
> pins connect.

I was thinking more about what I wrote and realized it lacked some context.

We created the soc_gen tool to stitch together the vhdl that goes into 
our soc. soc_gen generates some vhdl files (devices.vhd, soc.vhd, and 
pad_ring.vhd) which instantiate and wire together a bunch of 
hand-written vhdl.

Moving the uart pins isn't a good motivating example for using soc_gen. 
It would be simple to change the "loc" attributes for the two ports in 
pad_ring.vhd by hand, and by comparison it probably seems absurdly 
complicated to modify the edn file and install a JDK and leiningen. 
soc_gen starts to shine for more complicated changes and when 
maintaining multiple boards.

Instead of changing the pins connected to uart0_tx and uart0_tx, you 
might try adding a second uartlite named "uart1" to the :devices vector 
with a different memory mapped :base-addr. If you can get soc_gen to run 
without error, have a look at the differences in the generated vhdl.

- Geoff

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