[J-core] qemu support

Christopher Friedt chrisfriedt at gmail.com
Tue Apr 26 12:44:43 EDT 2016

Hi Rich,

Thanks for getting back to me.

Qemu is a pretty invaluable tool for getting people hacking on a new
architecture, if only because it lowers the barrier to entry in terms
of cost. Plus, it's sometimes a bit more convenient :-)

On Tue, Apr 26, 2016 at 12:23 PM, Rich Felker <dalias at libc.org> wrote:
> On Tue, Apr 26, 2016 at 08:15:58AM -0400, Christopher Friedt wrote:
>> Hi List,
>> just out of curiosity, has anyone started working on Qemu support for
>> j2 and e.g. the Numato board?
> No. It's something on my medium to long term agenda, but if somebody
> else wants to try sooner that would be great. I think it would make
> sense to start by converting qemu's sh support over to taking as input
> a device tree for the hardware to emulate rather than hard-coding a
> fixed board, but you could get by without this step.

Device Tree support would benefit not just sh or j2 but most
architectures in Qemu. I'm not even aware if DT support is available
currently for any arch in Qemu (PPC?). It would probably be best to
defer that, if that's the case, and then handle it for all machine

> The minimal change needed to run j2/sh2 bare-metal/kernel code (vs sh4
> code) is that the trap/interrupt mechanism has to jump to _code_ in
> the trap vector table rather than loading an address from the table.

Hmm... Is that specific to Qemu? Otherwise, maybe I'm unfamiliar with
the j2 / sh2 interrupt mechanism.

Do you know of a decent document describing the SuperH ISA and core model?

I have been working a bit on cortex-m support in qemu, so I assumed it
would be similar to that.


> Aside from that, support for the j2 cas.l (compare and swap)
> instruction should be added, and instructions not available on j2
> (i.e. all insns new on sh3+ except the barrel shifter) should be made
> to trap so that code that can't actually run on the real hardware gets
> caught.

Right - there is a -cpu argument that could be used to allow /
disallow certain instructions.


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