[J-core] Pondering j-core kickstarter ideas.
chrisfriedt at gmail.com
Mon Apr 25 12:26:56 EDT 2016
On Sun, Apr 24, 2016 at 2:50 PM, Rob Landley <rob at landley.net> wrote:
That's a *very* interesting video that you shared, by the way. I was
working on something similar for about 1.5 years until my company
decided to shelve the project. I have reserved various judgements
about those management decisions...
In any case,
> the result would be around 36,000 chips running around 250 mhz.
250 MHz is plenty for this sort of device, particularly with the SH2 /
J2 ISA being so dense (i.e. like Thumb / Thumb2).
> This means you can make SOC's for a little under $2/chip, but what we
> DIDN'T work out is what you'd do with those next.
> This is a tiny little chip (a couple milimeters on each side), which you
> could stick on the end of a USB or Ethernet connector, anything that
> provides both data and power. The question is, what would it take to
> wire the pins on the thing to the pins on say an ethernet connector,
> properly buffered so that passing insects don't fry your circuits? And
> what other stuff do you need to add (similarly tiny DRAM chips that our
> DRAM controller can talk to, etc).
> What would it take to make an actual, minimal hobbyist _device_?
Since nobody else has ponied up to give some feedback, I would
probably say that the best features to add are are on-chip peripherals
for short-range communication:
* (full) uart(s)
* obvioulsy a GPIO controller
* A2D / DAC
* as large a supported memory area as possible
* naturally on-chip clocks and timers are of course very useful
For the some of the above, we can naturally bit-bang those protocols,
but doing so would mean that CPU time for the application would be
spread thin. Having integrated controllers means less board space
occupied by external devices, but yes, it does mean that the analog
I/O stage must also be considered (i2c clock stretching, 3.3 / 5V I/O
voltage tolerance, for example).
For some things, e.g. ethernet, there are a number of discrete
ethernet MAC / PHY chips available too . Notice that SPI is a
very common interface for ethernet & wireless comms.
The more integrated peripherals the better (particularly embedded bus
peripherals), because that just lets people do more.
Possibly not for the initial fab, but future (more powerful) chips,
one consideration could be implementing peripheral controllers
themselves as embedded J2 cores (not in an SMP configuration) as an
alternative to e.g. Tensilica or opencores controllers. If we chose
J2, the firmware could be updatable rather than hard-coded in ROM, and
that would address some of the security issues brought up at ELC.
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