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<tt>Rich-san</tt><tt><br>
</tt><tt><br>
</tt><tt>I found that "Makefile is not generated by soc_gen";<br>
(they are manually written files)</tt><tt><br>
</tt><tt><br>
</tt><tt>[boards] $ fgrep lpddr microboard/Makefile</tt><tt><br>
</tt><tt><br>
</tt><tt>microboard/Makefile: DDR_TYPE=lpddr \</tt><tt><br>
</tt><tt><br>
</tt><tt>This controls boot/dev/ddr.c behavior.</tt><tt><br>
</tt><tt>When replace ddr controller to new one,</tt><tt><br>
</tt><tt>DDR_TYPE should be lpddr2 (instead of lpddr).</tt><tt><br>
</tt><tt>(note: here, lpddr lpddr2 does not link to memory device,
but</tt><tt><br>
</tt><tt> ddr controller. lpddr2 is for new ddr ctrl
(components/ddr2);</tt><tt><br>
</tt><tt> CL=3).</tt><tt><br>
</tt><tt><br>
When CL=2/3 does not match, OS will not boot.<br>
</tt><tt>I have not synthesized microboard with this modification.</tt><tt><br>
</tt><tt>Just as a comparison, lpddr2 is better.</tt><tt><br>
</tt><tt><br>
</tt><tt>Osamu Nishii</tt><br>
<br>
<div class="moz-cite-prefix">On 2016/10/24 11:02, Rich Felker wrote:<br>
</div>
<blockquote cite="mid:20161024020217.GA28032@brightrain.aerifal.cx"
type="cite">
<pre wrap="">As an exercise to learn a bit about soc_gen and stuff, I tried
enabling d/i cache for the old microboard target. Just adding the
cache_ctrl and changing:
- "ddr_ram_mux" {:architecture "one_cpu_direct"}
+ "ddr_ram_mux" {:configuration "ddr_ram_mux_one_cpu_idcache_fpga"}
produced errors at soc_gen time, so I tried switching to the new ddr
controller too, with the attached patch copied from similar changes to
mimas_v2, but the board just reboots as soon as the bootloader jumps
from sram to the loaded vmlinux. Any idea what I did wrong?
Rich
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