<html><head><meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body dir="auto"><div>Goran,</div><div><br></div><div>Can you tell us what the sticking point is? Is it integrated but not working, or is the problem knowing how to get it connected, configured and synthesised?</div><div><br></div><div>We will definitely look at your cores, we would very much like to build ecosystem. We have some thoughts on that... Geoff's SoC top level generator tool is proof that a high level of automation is both possible and useful...</div><div><br>Cheers,<div>J.</div></div><div><br>On Aug 24, 2016, at 17:49, Goran Mahovlić <<a href="mailto:goran.mahovlic@gmail.com">goran.mahovlic@gmail.com</a>> wrote:<br><br></div><blockquote type="cite"><div><div dir="ltr"><div><div>We still have no luck with implementing your DDR driver into our designs.<br></div><br>If someone have bit of time and could solve this, that would be great.<br><br>Recently he added Floating point vector processor, and some DDR3 AXI driver for other boards, but numato gives us trouble.<br><br><a href="https://github.com/f32c/f32c">https://github.com/f32c/f32c</a><br><br></div>And feel free to use our modules for your CORE to...<br><div><span style="color:rgb(0,0,0);font-family:Consolas,"Lucida Console",monospace;font-size:12.8px;background-color:rgb(240,247,255)"></span> </div></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jun 7, 2016 at 3:20 PM, Geoff Salmon <span dir="ltr"><<a href="mailto:gsalmon@se-instruments.com" target="_blank">gsalmon@se-instruments.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Goran<br>
<br>
CFG_DDR_CK_CYCLE = 20 in the mimas_v2 build. If you run a build you can see the values of these CFG_ and CONFIG_ values in the output directory's config sub-directory. You can build just the config files if you want too like this<br>
<br>
$ make mimas_v2 TARGET=config/config.vhd<br>
$ cat last_output/config/config.vhd<br>
-- This file is generated by the makefile<br>
package config is<br>
constant CFG_CLK_BITLINK_PERIOD_NS : integer := 8;<br>
constant CFG_CLK_CPU_DIVIDE : integer := 20;<br>
constant CFG_CLK_CPU_PERIOD_NS : integer := 20;<br>
constant CFG_CLK_MEM_2X_DIVIDE : integer := 10;<br>
constant CFG_CLK_MEM_PERIOD_NS : integer := 20;<br>
constant CFG_DDRDQ_WIDTH : integer := 16;<br>
constant CFG_DDR_CK_CYCLE : integer := 20;<br>
constant CFG_DDR_READ_SAMPLE_TM : integer := 2;<br>
constant CFG_SA_WIDTH : integer := 13;<br>
<br>
end;<br>
<br>
- Geoff<div><div class="h5"><br>
<br>
On 16-06-07 08:02 AM, Goran Mahovlić wrote:<br>
</div></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div class="h5">
My colege Emard is trying to fit your DDR driver to our f32c core, so if<br>
you can help him a bit.<br>
Does someone know what should be constant value for numato<br>
<br>
CFG_DDR_CK_CYCLE = ?<br>
<br>
Tnx ,<br>
Goran<br>
<br>
<br></div></div>
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</blockquote>
<br>
<br>
</blockquote></div><br></div>
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