*** Running vivado with args -log cpu.vdi -applog -m64 -messageDb vivado.pb -mode batch -source cpu.tcl -notrace ****** Vivado v2015.1 (64-bit) **** SW Build 1215546 on Mon Apr 27 19:22:08 MDT 2015 **** IP Build 1209967 on Tue Apr 21 11:39:20 MDT 2015 ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. source cpu.tcl -notrace Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Netlist 29-17] Analyzing 184 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2015.1 INFO: [Device 21-403] Loading part xc7k325tffg900-2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 12 instances were transformed. RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 12 instances link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 525.262 ; gain = 299.684 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.149 . Memory (MB): peak = 531.398 ; gain = 2.055 INFO: [Timing 38-35] Done setting XDC timing constraints. Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 12c86ccca Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.253 . Memory (MB): peak = 986.188 ; gain = 0.000 Phase 2 Constant Propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-10] Eliminated 0 cells. Phase 2 Constant Propagation | Checksum: 12c86ccca Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.406 . Memory (MB): peak = 986.188 ; gain = 0.000 Phase 3 Sweep INFO: [Opt 31-12] Eliminated 192 unconnected nets. INFO: [Opt 31-11] Eliminated 0 unconnected cells. Phase 3 Sweep | Checksum: f0cdb455 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.635 . Memory (MB): peak = 986.188 ; gain = 0.000 Starting Connectivity Check Task Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 986.188 ; gain = 0.000 Ending Logic Optimization Task | Checksum: f0cdb455 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.654 . Memory (MB): peak = 986.188 ; gain = 0.000 Implement Debug Cores | Checksum: 1002bfcc6 Logic Optimization | Checksum: 1002bfcc6 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 3.13 ns. Ending Power Optimization Task | Checksum: f0cdb455 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 986.188 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 986.188 ; gain = 460.926 INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/sgutierrez/j2_cpu/j2_cpu.runs/impl_1/cpu_drc_opted.rpt. Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs Phase 1 Placer Runtime Estimator Phase 1 Placer Runtime Estimator | Checksum: 795df8fb Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.097 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 2 Placer Initialization Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1055.305 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 2.1 IO Placement/ Clock Placement/ Build Placer Device Phase 2.1.1 Pre-Place Cells Phase 2.1.1 Pre-Place Cells | Checksum: 00000000 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.208 . Memory (MB): peak = 1055.305 ; gain = 0.000 INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 2.1.2 IO & Clk Clean Up Phase 2.1.2 IO & Clk Clean Up | Checksum: 00000000 Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 2.1.3 Implementation Feasibility check On IDelay Phase 2.1.3 Implementation Feasibility check On IDelay | Checksum: 00000000 Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 2.1.4 Commit IO Placement Phase 2.1.4 Commit IO Placement | Checksum: d95f4c95 Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 2.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 112e15478 Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 2.2 Build Placer Netlist Model Phase 2.2.1 Place Init Design Phase 2.2.1 Place Init Design | Checksum: 11e073b85 Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 2.2 Build Placer Netlist Model | Checksum: 11e073b85 Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 2.3 Constrain Clocks/Macros Phase 2.3.1 Constrain Global/Regional Clocks Phase 2.3.1 Constrain Global/Regional Clocks | Checksum: 11e073b85 Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 2.3 Constrain Clocks/Macros | Checksum: 11e073b85 Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 2 Placer Initialization | Checksum: 11e073b85 Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 3 Global Placement Phase 3 Global Placement | Checksum: 51f7c727 Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 4 Detail Placement Phase 4.1 Commit Multi Column Macros Phase 4.1 Commit Multi Column Macros | Checksum: 51f7c727 Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 4.2 Commit Most Macros & LUTRAMs Phase 4.2 Commit Most Macros & LUTRAMs | Checksum: 12a3eceeb Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 4.3 Area Swap Optimization Phase 4.3 Area Swap Optimization | Checksum: 11619e1dd Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 4.4 Small Shape Detail Placement Phase 4.4.1 Commit Small Macros & Core Logic Phase 4.4.1.1 Commit Slice Clusters Phase 4.4.1.1 Commit Slice Clusters | Checksum: 18afaad98 Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 4.4.1 Commit Small Macros & Core Logic | Checksum: 18afaad98 Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 4.4.2 Clock Restriction Legalization for Leaf Columns Phase 4.4.2 Clock Restriction Legalization for Leaf Columns | Checksum: 18afaad98 Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 4.4.3 Clock Restriction Legalization for Non-Clock Pins Phase 4.4.3 Clock Restriction Legalization for Non-Clock Pins | Checksum: 18afaad98 Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 4.4 Small Shape Detail Placement | Checksum: 18afaad98 Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 4.5 Re-assign LUT pins Phase 4.5 Re-assign LUT pins | Checksum: 18afaad98 Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 4 Detail Placement | Checksum: 18afaad98 Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 5 Post Placement Optimization and Clean-Up Phase 5.1 PCOPT Shape updates Phase 5.1 PCOPT Shape updates | Checksum: 2585505c8 Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 5.2 Post Commit Optimization Phase 5.2 Post Commit Optimization | Checksum: 2585505c8 Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 5.3 Sweep Clock Roots: Post-Placement Phase 5.3 Sweep Clock Roots: Post-Placement | Checksum: 2585505c8 Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 5.4 Post Placement Cleanup Phase 5.4 Post Placement Cleanup | Checksum: 2585505c8 Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 5.5 Placer Reporting Phase 5.5 Placer Reporting | Checksum: 2585505c8 Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 5.6 Final Placement Cleanup Phase 5.6 Final Placement Cleanup | Checksum: 1b4159e26 Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 1055.305 ; gain = 0.000 Phase 5 Post Placement Optimization and Clean-Up | Checksum: 1b4159e26 Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 1055.305 ; gain = 0.000 Ending Placer Task | Checksum: 131b9e5da Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 1055.305 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 32 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1055.305 ; gain = 1.996 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.599 . Memory (MB): peak = 1055.305 ; gain = 0.000 report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.148 . Memory (MB): peak = 1055.305 ; gain = 0.000 report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.198 . Memory (MB): peak = 1055.305 ; gain = 0.000 report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1055.305 ; gain = 0.000 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 1d77de104 Time (s): cpu = 00:01:47 ; elapsed = 00:01:33 . Memory (MB): peak = 1297.852 ; gain = 204.266 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Pre Route Cleanup Phase 2.1 Pre Route Cleanup | Checksum: 1d77de104 Time (s): cpu = 00:01:47 ; elapsed = 00:01:33 . Memory (MB): peak = 1302.738 ; gain = 209.152 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 7274a6e5 Time (s): cpu = 00:01:48 ; elapsed = 00:01:34 . Memory (MB): peak = 1345.121 ; gain = 251.535 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 13d1e6c1c Time (s): cpu = 00:01:50 ; elapsed = 00:01:35 . Memory (MB): peak = 1345.121 ; gain = 251.535 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 520 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 Phase 4.1 Global Iteration 0 | Checksum: aad11096 Time (s): cpu = 00:01:52 ; elapsed = 00:01:35 . Memory (MB): peak = 1345.121 ; gain = 251.535 Phase 4 Rip-up And Reroute | Checksum: aad11096 Time (s): cpu = 00:01:52 ; elapsed = 00:01:36 . Memory (MB): peak = 1345.121 ; gain = 251.535 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: aad11096 Time (s): cpu = 00:01:52 ; elapsed = 00:01:36 . Memory (MB): peak = 1345.121 ; gain = 251.535 Phase 6 Post Hold Fix Phase 6 Post Hold Fix | Checksum: aad11096 Time (s): cpu = 00:01:52 ; elapsed = 00:01:36 . Memory (MB): peak = 1345.121 ; gain = 251.535 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.485536 % Global Horizontal Routing Utilization = 0.318041 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 42.3423%, No Congested Regions. South Dir 1x1 Area, Max Cong = 45.045%, No Congested Regions. East Dir 1x1 Area, Max Cong = 47.0588%, No Congested Regions. West Dir 1x1 Area, Max Cong = 52.9412%, No Congested Regions. Phase 7 Route finalize | Checksum: aad11096 Time (s): cpu = 00:01:52 ; elapsed = 00:01:36 . Memory (MB): peak = 1345.121 ; gain = 251.535 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: aad11096 Time (s): cpu = 00:01:52 ; elapsed = 00:01:36 . Memory (MB): peak = 1345.121 ; gain = 251.535 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: d7aad694 Time (s): cpu = 00:01:52 ; elapsed = 00:01:36 . Memory (MB): peak = 1345.121 ; gain = 251.535 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:01:52 ; elapsed = 00:01:36 . Memory (MB): peak = 1345.121 ; gain = 251.535 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 40 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:01:54 ; elapsed = 00:01:38 . Memory (MB): peak = 1345.121 ; gain = 289.816 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.682 . Memory (MB): peak = 1345.121 ; gain = 0.000 INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/sgutierrez/j2_cpu/j2_cpu.runs/impl_1/cpu_drc_routed.rpt. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. WARNING: [Power 33-232] No user defined clocks were found in the design! Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Common 17-206] Exiting Vivado at Fri Jun 17 12:04:45 2016... *** Running vivado with args -log cpu.vdi -applog -m64 -messageDb vivado.pb -mode batch -source cpu.tcl -notrace ****** Vivado v2015.1 (64-bit) **** SW Build 1215546 on Mon Apr 27 19:22:08 MDT 2015 **** IP Build 1209967 on Tue Apr 21 11:39:20 MDT 2015 ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. source cpu.tcl -notrace Command: open_checkpoint cpu_routed.dcp INFO: [Netlist 29-17] Analyzing 184 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2015.1 INFO: [Device 21-403] Loading part xc7k325tffg900-2 INFO: [Project 1-570] Preparing netlist for logic optimization Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.454 . Memory (MB): peak = 522.172 ; gain = 5.426 Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.455 . Memory (MB): peak = 522.172 ; gain = 5.426 INFO: [Project 1-111] Unisim Transformation Summary: A total of 12 instances were transformed. RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 12 instances INFO: [Project 1-484] Checkpoint was created with build 1215546 open_checkpoint: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 523.094 ; gain = 330.895 Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' Running DRC as a precondition to command write_bitstream INFO: [DRC 23-27] Running DRC with 2 threads ERROR: [DRC 23-20] Rule violation (LUTLP-1) Combinatorial Loop - 3 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. To allow bitstream creation for designs with combinatorial logic loops (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. u_datapath/u_regfile/this_r[id_stall]_i_1, u_decode/core/this_r[id_stall]_i_5, u_decode/core/this_r[sr][t]_i_1. ERROR: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 266 out of 266 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: db_o[a][31:0], db_o[we][3:0], db_o[d][31:0], db_i[d][31:0], inst_o[a][31:1], inst_i[d][15:0], debug_o[d][31:0], debug_i[cmd][1:0], debug_i[ir][15:0], debug_i[d][31:0], event_o[lvl][3:0], event_i[cmd][1:0], event_i[vec][7:0], event_i[lvl][3:0], clk (the first 15 of 33 listed). ERROR: [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 266 out of 266 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: db_o[a][31:0], db_o[we][3:0], db_o[d][31:0], db_i[d][31:0], inst_o[a][31:1], inst_i[d][15:0], debug_o[d][31:0], debug_i[cmd][1:0], debug_i[ir][15:0], debug_i[d][31:0], event_o[lvl][3:0], event_i[cmd][1:0], event_i[vec][7:0], event_i[lvl][3:0], clk (the first 15 of 33 listed). WARNING: [DRC 23-20] Rule violation (CFGBVS-1) Missing CFGBVS and CONFIG_VOLTAGE Design Properties - Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_mult/this_r_reg[abh]0 input A B is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP u_mult/this_r_reg[abh]0__0 input A B is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_mult/this_r_reg[abh]0 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP u_mult/this_r_reg[abh]0__0 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. WARNING: [DRC 23-20] Rule violation (DPOR-1) Asynchronous load check - DSP u_mult/this_r_reg[abh]0 output is connected to asynchronous registers (u_mult/this_r_reg[abh][0], u_mult/this_r_reg[abh][1], u_mult/this_r_reg[abh][2], u_mult/this_r_reg[abh][3], u_mult/this_r_reg[abh][4], u_mult/this_r_reg[abh][5], u_mult/this_r_reg[abh][6], u_mult/this_r_reg[abh][7], u_mult/this_r_reg[abh][8], u_mult/this_r_reg[abh][9], u_mult/this_r_reg[abh][10], u_mult/this_r_reg[abh][11], u_mult/this_r_reg[abh][12], u_mult/this_r_reg[abh][13], u_mult/this_r_reg[abh][14] (the first 15 of 17 listed)). If you use synchronous controls you will get better results both in area and delay (DSP48 has synchronous registers built in). INFO: [Vivado 12-3199] DRC finished with 3 Errors, 6 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. INFO: [Common 17-83] Releasing license: Implementation ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors. INFO: [Common 17-206] Exiting Vivado at Fri Jun 17 12:05:40 2016...