*** Running vivado with args -log cpu.vds -m64 -mode batch -messageDb vivado.pb -notrace -source cpu.tcl ****** Vivado v2015.1 (64-bit) **** SW Build 1215546 on Mon Apr 27 19:22:08 MDT 2015 **** IP Build 1209967 on Tue Apr 21 11:39:20 MDT 2015 ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. source cpu.tcl -notrace Command: synth_design -top cpu -part xc7k325tffg900-2 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 272.473 ; gain = 95.051 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'cpu' [C:/Users/sgutierrez/j2_cpu/core/cpu.vhd:26] ERROR: [Synth 8-493] no such design unit 'cpu_decode_reverse' [C:/Users/sgutierrez/j2_cpu/core/cpu.vhd:53] ERROR: [Synth 8-285] failed synthesizing module 'cpu' [C:/Users/sgutierrez/j2_cpu/core/cpu.vhd:26] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 310.746 ; gain = 133.324 --------------------------------------------------------------------------------- synthesize failed INFO: [Common 17-83] Releasing license: Synthesis 3 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered. synth_design failed ERROR: [Common 17-69] Command failed: Vivado Synthesis failed INFO: [Common 17-206] Exiting Vivado at Fri Jun 17 11:55:30 2016...