*** Running vivado with args -log cpu_core.vds -m64 -mode batch -messageDb vivado.pb -notrace -source cpu_core.tcl ****** Vivado v2015.1 (64-bit) **** SW Build 1215546 on Mon Apr 27 19:22:08 MDT 2015 **** IP Build 1209967 on Tue Apr 21 11:39:20 MDT 2015 ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. source cpu_core.tcl -notrace Command: synth_design -top cpu_core -part xc7k325tffg900-2 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 272.609 ; gain = 94.918 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'cpu_core' [C:/Users/sgutierrez/_j2/j2_cpu_core/cpu_core.vhd:48] Parameter bus_period bound to: 32 - type: integer INFO: [Synth 8-3491] module 'cpu' declared at 'C:/Users/sgutierrez/_j2/j2_cpu_core/core/cpu.vhd:12' bound to instance 'u_cpu' of component 'cpu' [C:/Users/sgutierrez/_j2/j2_cpu_core/cpu_core.vhd:66] INFO: [Synth 8-638] synthesizing module 'cpu' [C:/Users/sgutierrez/_j2/j2_cpu_core/core/cpu.vhd:26] INFO: [Synth 8-3491] module 'decode' declared at 'C:/Users/sgutierrez/_j2/j2_cpu_core/decode/decode.vhd:17' bound to instance 'u_decode' of component 'decode' [C:/Users/sgutierrez/_j2/j2_cpu_core/core/cpu.vhd:53] INFO: [Synth 8-638] synthesizing module 'decode' [C:/Users/sgutierrez/_j2/j2_cpu_core/decode/decode.vhd:45] Parameter decode_type bound to: 1 - type: integer Parameter reset_vector bound to: 33'b000010000001100000000000000010000 INFO: [Synth 8-3491] module 'decode_core' declared at 'C:/Users/sgutierrez/_j2/j2_cpu_core/decode/decode_core.vhd:8' bound to instance 'core' of component 'decode_core' [C:/Users/sgutierrez/_j2/j2_cpu_core/decode/decode.vhd:71] INFO: [Synth 8-638] synthesizing module 'decode_core' [C:/Users/sgutierrez/_j2/j2_cpu_core/decode/decode_core.vhd:45] Parameter decode_type bound to: 1 - type: integer Parameter reset_vector bound to: 33'b000010000001100000000000000010000 INFO: [Synth 8-256] done synthesizing module 'decode_core' (1#1) [C:/Users/sgutierrez/_j2/j2_cpu_core/decode/decode_core.vhd:45] INFO: [Synth 8-3491] module 'decode_table' declared at 'C:/Users/sgutierrez/_j2/j2_cpu_core/decode/decode_table.vhd:16' bound to instance 'table' of component 'decode_table' [C:/Users/sgutierrez/_j2/j2_cpu_core/decode/decode.vhd:107] INFO: [Synth 8-638] synthesizing module 'decode_table' [C:/Users/sgutierrez/_j2/j2_cpu_core/decode/decode_table.vhd:39] INFO: [Synth 8-256] done synthesizing module 'decode_table' (2#1) [C:/Users/sgutierrez/_j2/j2_cpu_core/decode/decode_table.vhd:39] INFO: [Synth 8-256] done synthesizing module 'decode' (3#1) [C:/Users/sgutierrez/_j2/j2_cpu_core/decode/decode.vhd:45] INFO: [Synth 8-3491] module 'mult' declared at 'C:/Users/sgutierrez/_j2/j2_cpu_core/core/mult.vhd:7' bound to instance 'u_mult' of component 'mult' [C:/Users/sgutierrez/_j2/j2_cpu_core/core/cpu.vhd:68] INFO: [Synth 8-638] synthesizing module 'mult' [C:/Users/sgutierrez/_j2/j2_cpu_core/core/mult.vhd:14] INFO: [Synth 8-256] done synthesizing module 'mult' (4#1) [C:/Users/sgutierrez/_j2/j2_cpu_core/core/mult.vhd:14] INFO: [Synth 8-3491] module 'datapath' declared at 'C:/Users/sgutierrez/_j2/j2_cpu_core/core/datapath.vhd:10' bound to instance 'u_datapath' of component 'datapath' [C:/Users/sgutierrez/_j2/j2_cpu_core/core/cpu.vhd:72] INFO: [Synth 8-638] synthesizing module 'datapath' [C:/Users/sgutierrez/_j2/j2_cpu_core/core/datapath.vhd:46] INFO: [Synth 8-638] synthesizing module 'register_file_two_bank' [C:/Users/sgutierrez/_j2/j2_cpu_core/core/register_file.vhd:107] Parameter ADDR_WIDTH bound to: 5 - type: integer Parameter NUM_REGS bound to: 21 - type: integer Parameter REG_WIDTH bound to: 32 - type: integer INFO: [Synth 8-63] RTL assertion: "Register out of range" [C:/Users/sgutierrez/_j2/j2_cpu_core/core/register_file.vhd:100] INFO: [Synth 8-63] RTL assertion: "Register out of range" [C:/Users/sgutierrez/_j2/j2_cpu_core/core/register_file.vhd:100] WARNING: [Synth 8-312] ignoring unsynthesizable construct: assertion statement [C:/Users/sgutierrez/_j2/j2_cpu_core/core/register_file.vhd:137] INFO: [Synth 8-63] RTL assertion: "Register out of range" [C:/Users/sgutierrez/_j2/j2_cpu_core/core/register_file.vhd:100] INFO: [Synth 8-63] RTL assertion: "Register out of range" [C:/Users/sgutierrez/_j2/j2_cpu_core/core/register_file.vhd:100] INFO: [Synth 8-256] done synthesizing module 'register_file_two_bank' (5#1) [C:/Users/sgutierrez/_j2/j2_cpu_core/core/register_file.vhd:107] INFO: [Synth 8-256] done synthesizing module 'datapath' (6#1) [C:/Users/sgutierrez/_j2/j2_cpu_core/core/datapath.vhd:46] INFO: [Synth 8-256] done synthesizing module 'cpu' (7#1) [C:/Users/sgutierrez/_j2/j2_cpu_core/core/cpu.vhd:26] Parameter c_busperiod bound to: 32 - type: integer INFO: [Synth 8-3491] module 'aic' declared at 'C:/Users/sgutierrez/_j2/j2_cpu_core/aic.vhd:10' bound to instance 'u_aic' of component 'aic' [C:/Users/sgutierrez/_j2/j2_cpu_core/cpu_core.vhd:113] INFO: [Synth 8-638] synthesizing module 'aic' [C:/Users/sgutierrez/_j2/j2_cpu_core/aic.vhd:29] Parameter c_busperiod bound to: 32 - type: integer INFO: [Synth 8-3491] module 'aic_edgedet' declared at 'C:/Users/sgutierrez/_j2/j2_cpu_core/aic_edgedet.vhd:9' bound to instance 'iedge_inst' of component 'aic_edgedet' [C:/Users/sgutierrez/_j2/j2_cpu_core/aic.vhd:83] INFO: [Synth 8-638] synthesizing module 'aic_edgedet' [C:/Users/sgutierrez/_j2/j2_cpu_core/aic_edgedet.vhd:17] INFO: [Synth 8-256] done synthesizing module 'aic_edgedet' (8#1) [C:/Users/sgutierrez/_j2/j2_cpu_core/aic_edgedet.vhd:17] INFO: [Synth 8-3491] module 'aic_edgedet' declared at 'C:/Users/sgutierrez/_j2/j2_cpu_core/aic_edgedet.vhd:9' bound to instance 'iedge_inst' of component 'aic_edgedet' [C:/Users/sgutierrez/_j2/j2_cpu_core/aic.vhd:83] INFO: [Synth 8-3491] module 'aic_edgedet' declared at 'C:/Users/sgutierrez/_j2/j2_cpu_core/aic_edgedet.vhd:9' bound to instance 'iedge_inst' of component 'aic_edgedet' [C:/Users/sgutierrez/_j2/j2_cpu_core/aic.vhd:83] INFO: [Synth 8-3491] module 'aic_edgedet' declared at 'C:/Users/sgutierrez/_j2/j2_cpu_core/aic_edgedet.vhd:9' bound to instance 'iedge_inst' of component 'aic_edgedet' [C:/Users/sgutierrez/_j2/j2_cpu_core/aic.vhd:83] INFO: [Synth 8-3491] module 'aic_edgedet' declared at 'C:/Users/sgutierrez/_j2/j2_cpu_core/aic_edgedet.vhd:9' bound to instance 'iedge_inst' of component 'aic_edgedet' [C:/Users/sgutierrez/_j2/j2_cpu_core/aic.vhd:83] INFO: [Synth 8-3491] module 'aic_edgedet' declared at 'C:/Users/sgutierrez/_j2/j2_cpu_core/aic_edgedet.vhd:9' bound to instance 'iedge_inst' of component 'aic_edgedet' [C:/Users/sgutierrez/_j2/j2_cpu_core/aic.vhd:83] INFO: [Synth 8-3491] module 'aic_edgedet' declared at 'C:/Users/sgutierrez/_j2/j2_cpu_core/aic_edgedet.vhd:9' bound to instance 'iedge_inst' of component 'aic_edgedet' [C:/Users/sgutierrez/_j2/j2_cpu_core/aic.vhd:83] INFO: [Synth 8-3491] module 'aic_edgedet' declared at 'C:/Users/sgutierrez/_j2/j2_cpu_core/aic_edgedet.vhd:9' bound to instance 'iedge_inst' of component 'aic_edgedet' [C:/Users/sgutierrez/_j2/j2_cpu_core/aic.vhd:83] INFO: [Synth 8-256] done synthesizing module 'aic' (9#1) [C:/Users/sgutierrez/_j2/j2_cpu_core/aic.vhd:29] INFO: [Synth 8-256] done synthesizing module 'cpu_core' (10#1) [C:/Users/sgutierrez/_j2/j2_cpu_core/cpu_core.vhd:48] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 339.676 ; gain = 161.984 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 339.676 ; gain = 161.984 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k325tffg900-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 339.676 ; gain = 161.984 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7k325tffg900-2 ROM size is below threshold of ROM address width. It will be mapped to LUTs ROM size is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5544] ROM "ex[aluinx_sel]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) ROM size is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5544] ROM "ex[logic_func]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "mac_busy" won't be mapped to Block RAM because address size (3) smaller than threshold (5) ROM size is below threshold of ROM address width. It will be mapped to LUTs ROM size is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5544] ROM "ex_stall[t_sel]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "ex_stall[shiftfunc]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) ROM size is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5544] ROM "sat" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sat" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sat" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sat" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5545] ROM "reg0" won't be mapped to RAM because address size (32) is larger than maximum supported(18) INFO: [Synth 8-5544] ROM "this[debug_o][rdy]" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "rot" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5546] ROM "check_illegal_instruction" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "id_irq[0]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "v_irq[0]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "vstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5) INFO: [Synth 8-5544] ROM "decode_core_instr_addr" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5545] ROM "decode_core_data_addr" won't be mapped to RAM because address size (20) is larger than maximum supported(18) INFO: [Synth 8-5544] ROM "event_i[en]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "event_i[cmd]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "event_i[msk]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 513.664 ; gain = 335.973 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 64 Bit Adders := 2 3 Input 33 Bit Adders := 2 2 Input 32 Bit Adders := 5 2 Input 21 Bit Adders := 1 2 Input 8 Bit Adders := 1 2 Input 4 Bit Adders := 1 +---XORs : 2 Input 32 Bit XORs := 4 2 Input 4 Bit XORs := 1 2 Input 1 Bit XORs := 37 3 Input 1 Bit XORs := 1 +---Registers : 64 Bit Registers := 1 48 Bit Registers := 2 32 Bit Registers := 25 31 Bit Registers := 1 25 Bit Registers := 1 21 Bit Registers := 1 16 Bit Registers := 3 12 Bit Registers := 1 11 Bit Registers := 1 8 Bit Registers := 2 5 Bit Registers := 13 4 Bit Registers := 13 3 Bit Registers := 5 2 Bit Registers := 20 1 Bit Registers := 99 +---RAMs : 672 Bit RAMs := 2 +---Muxes : 2 Input 64 Bit Muxes := 10 4 Input 64 Bit Muxes := 1 3 Input 64 Bit Muxes := 2 2 Input 33 Bit Muxes := 2 2 Input 32 Bit Muxes := 84 3 Input 32 Bit Muxes := 2 4 Input 32 Bit Muxes := 9 2 Input 31 Bit Muxes := 9 8 Input 25 Bit Muxes := 1 4 Input 21 Bit Muxes := 1 5 Input 16 Bit Muxes := 1 2 Input 16 Bit Muxes := 10 4 Input 16 Bit Muxes := 1 3 Input 16 Bit Muxes := 1 2 Input 8 Bit Muxes := 3 4 Input 8 Bit Muxes := 2 8 Input 8 Bit Muxes := 1 6 Input 8 Bit Muxes := 1 8 Input 5 Bit Muxes := 5 6 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 7 3 Input 5 Bit Muxes := 1 22 Input 5 Bit Muxes := 1 3 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 20 8 Input 4 Bit Muxes := 1 12 Input 4 Bit Muxes := 1 6 Input 3 Bit Muxes := 2 8 Input 3 Bit Muxes := 8 4 Input 3 Bit Muxes := 1 7 Input 3 Bit Muxes := 1 2 Input 3 Bit Muxes := 17 5 Input 3 Bit Muxes := 1 3 Input 2 Bit Muxes := 4 4 Input 2 Bit Muxes := 10 2 Input 2 Bit Muxes := 47 6 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 139 4 Input 1 Bit Muxes := 20 3 Input 1 Bit Muxes := 3 21 Input 1 Bit Muxes := 1 9 Input 1 Bit Muxes := 1 15 Input 1 Bit Muxes := 2 8 Input 1 Bit Muxes := 5 5 Input 1 Bit Muxes := 4 6 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module cpu_core Detailed RTL Component Info : +---Muxes : 3 Input 16 Bit Muxes := 1 5 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module decode_core Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 16 Bit Registers := 1 8 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 5 Input 16 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module decode_table Detailed RTL Component Info : +---Muxes : 8 Input 5 Bit Muxes := 4 6 Input 5 Bit Muxes := 1 3 Input 4 Bit Muxes := 1 6 Input 3 Bit Muxes := 2 8 Input 3 Bit Muxes := 8 4 Input 3 Bit Muxes := 1 7 Input 3 Bit Muxes := 1 3 Input 2 Bit Muxes := 4 4 Input 2 Bit Muxes := 4 4 Input 1 Bit Muxes := 3 2 Input 1 Bit Muxes := 1 3 Input 1 Bit Muxes := 2 Module decode Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 5 Bit Registers := 10 3 Bit Registers := 5 2 Bit Registers := 16 1 Bit Registers := 33 +---Muxes : 2 Input 5 Bit Muxes := 3 2 Input 3 Bit Muxes := 3 2 Input 2 Bit Muxes := 9 Module mult Detailed RTL Component Info : +---Adders : 2 Input 64 Bit Adders := 1 3 Input 33 Bit Adders := 1 2 Input 32 Bit Adders := 1 +---XORs : 2 Input 32 Bit XORs := 1 +---Registers : 48 Bit Registers := 2 32 Bit Registers := 6 5 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 64 Bit Muxes := 6 4 Input 64 Bit Muxes := 1 3 Input 64 Bit Muxes := 2 2 Input 33 Bit Muxes := 2 2 Input 32 Bit Muxes := 6 2 Input 31 Bit Muxes := 4 2 Input 16 Bit Muxes := 3 2 Input 5 Bit Muxes := 2 3 Input 5 Bit Muxes := 1 22 Input 5 Bit Muxes := 1 21 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 4 Input 1 Bit Muxes := 1 9 Input 1 Bit Muxes := 1 Module register_file_two_bank Detailed RTL Component Info : +---Registers : 32 Bit Registers := 4 5 Bit Registers := 2 1 Bit Registers := 2 +---RAMs : 672 Bit RAMs := 2 +---Muxes : 2 Input 32 Bit Muxes := 12 2 Input 5 Bit Muxes := 2 Module datapath Detailed RTL Component Info : +---Adders : 3 Input 33 Bit Adders := 1 2 Input 32 Bit Adders := 1 +---XORs : 2 Input 32 Bit XORs := 3 2 Input 4 Bit XORs := 1 2 Input 1 Bit XORs := 37 3 Input 1 Bit XORs := 1 +---Registers : 32 Bit Registers := 10 31 Bit Registers := 1 16 Bit Registers := 2 4 Bit Registers := 3 2 Bit Registers := 2 1 Bit Registers := 21 +---Muxes : 3 Input 32 Bit Muxes := 2 2 Input 32 Bit Muxes := 49 4 Input 32 Bit Muxes := 8 2 Input 31 Bit Muxes := 5 2 Input 16 Bit Muxes := 6 4 Input 16 Bit Muxes := 1 4 Input 8 Bit Muxes := 2 2 Input 4 Bit Muxes := 7 8 Input 4 Bit Muxes := 1 12 Input 4 Bit Muxes := 1 2 Input 2 Bit Muxes := 36 4 Input 2 Bit Muxes := 5 2 Input 1 Bit Muxes := 88 4 Input 1 Bit Muxes := 10 15 Input 1 Bit Muxes := 2 8 Input 1 Bit Muxes := 5 Module aic_edgedet Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 2 Input 1 Bit Muxes := 1 Module aic Detailed RTL Component Info : +---Adders : 2 Input 64 Bit Adders := 1 2 Input 32 Bit Adders := 3 2 Input 21 Bit Adders := 1 2 Input 4 Bit Adders := 1 +---Registers : 64 Bit Registers := 1 32 Bit Registers := 4 25 Bit Registers := 1 21 Bit Registers := 1 12 Bit Registers := 1 11 Bit Registers := 1 8 Bit Registers := 1 4 Bit Registers := 9 2 Bit Registers := 1 1 Bit Registers := 13 +---Muxes : 2 Input 64 Bit Muxes := 4 2 Input 32 Bit Muxes := 17 4 Input 32 Bit Muxes := 1 8 Input 25 Bit Muxes := 1 4 Input 21 Bit Muxes := 1 8 Input 8 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 6 Input 8 Bit Muxes := 1 8 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 13 2 Input 3 Bit Muxes := 14 6 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 29 5 Input 1 Bit Muxes := 4 6 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 6 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 840 (col length:140) BRAMs: 890 (col length: RAMB18 140 RAMB36 70) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Start Parallel Synthesis Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 513.664 ; gain = 335.973 --------------------------------------------------------------------------------- Start Cross Boundary Optimization --------------------------------------------------------------------------------- ROM size is below threshold of ROM address width. It will be mapped to LUTs ROM size is below threshold of ROM address width. It will be mapped to LUTs DSP Report: Generating DSP this_r_reg[abh]0, operation Mode is: A*B. DSP Report: operator this_r_reg[abh]0 is absorbed into DSP this_r_reg[abh]0. DSP Report: operator this_r_reg[abh]0 is absorbed into DSP this_r_reg[abh]0. DSP Report: Generating DSP this_r_reg[abh]0, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator this_r_reg[abh]0 is absorbed into DSP this_r_reg[abh]0. DSP Report: operator this_r_reg[abh]0 is absorbed into DSP this_r_reg[abh]0. INFO: [Synth 8-5545] ROM "reg0" won't be mapped to RAM because address size (32) is larger than maximum supported(18) INFO: [Synth 8-5546] ROM "check_illegal_instruction" won't be mapped to RAM because it is too sparse --------------------------------------------------------------------------------- Finished Cross Boundary Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 527.547 ; gain = 349.855 --------------------------------------------------------------------------------- Finished Parallel Reinference : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 527.547 ; gain = 349.855 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- ROM: +------------+------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------+------------+---------------+----------------+ |mult | rom | 32x1 | LUT | |mult | rom__1 | 32x1 | LUT | |mult | rom__2 | 32x1 | LUT | |mult | rom__3 | 32x1 | LUT | |mult | rom__4 | 32x1 | LUT | |mult | rom__5 | 32x1 | LUT | |mult | rom__6 | 32x1 | LUT | |mult | rom | 32x1 | LUT | |mult | rom__7 | 32x1 | LUT | |mult | rom__8 | 32x1 | LUT | |mult | rom__9 | 32x1 | LUT | |mult | rom__10 | 32x1 | LUT | |mult | rom__11 | 32x1 | LUT | |mult | rom__12 | 32x1 | LUT | +------------+------------+---------------+----------------+ Distributed RAM: +------------+------------+-----------+----------------------+--------------+-------------------------------------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | Hierarchical Name | +------------+------------+-----------+----------------------+--------------+-------------------------------------------------+ |cpu_core | bank_a_reg | Implied | 32 x 32 | RAM32M x 6 | cpu_core/datapath/register_file_two_bank/ram__2 | |cpu_core | bank_b_reg | Implied | 32 x 32 | RAM32M x 6 | cpu_core/datapath/register_file_two_bank/ram__3 | +------------+------------+-----------+----------------------+--------------+-------------------------------------------------+ Note: The table shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. "Hierarchical Name" reflects the Distributed RAM name as it appears in the hierarchical module and only part of it is displayed. DSP: +------------+----------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |Module Name | DSP Mapping | Neg Edge Clk | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | +------------+----------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |mult | A*B | No | 18 | 17 | 48 | 25 | 48 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | |mult | (PCIN>>17)+A*B | No | 17 | 15 | 31 | 25 | 48 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | +------------+----------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ Note: The table shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- No constraint files found. INFO: [Synth 8-3333] propagating constant 0 across sequential element (\u_cpu/u_decode /\pipeline_r_reg[ex1_stall][macsel1][1] ) WARNING: [Synth 8-3332] Sequential element (\core/this_r_reg[op][addr][7] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\core/this_r_reg[op][addr][6] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\core/this_r_reg[op][addr][5] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\core/this_r_reg[op][addr][4] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][30] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][29] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][28] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][27] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][26] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][25] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][24] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][23] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][22] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][21] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][20] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][19] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][18] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][17] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][16] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][15] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][14] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][13] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1][imm_val][12] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[wb1_stall][mulcom2][0] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[wb2_stall][mulcom2][0] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[wb3_stall][mulcom2][0] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1_stall][wrsr_z] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1_stall][macsel2][1] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[wb1_stall][macsel2][0] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[wb1_stall][macsel1][0] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[wb1_stall][mulcom2][4] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[wb2_stall][mulcom2][4] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[wb2_stall][macsel2][0] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[wb2_stall][macsel1][0] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[ex1_stall][macsel1][1] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[wb3_stall][macsel1][0] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[wb3_stall][macsel2][0] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\pipeline_r_reg[wb3_stall][mulcom2][4] ) is unused and will be removed from module decode. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][47] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][46] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][45] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][44] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][43] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][42] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][41] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][40] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][39] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][38] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][37] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][36] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][35] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][34] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][33] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][32] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][31] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][30] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][29] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][28] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][27] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][26] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][25] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][24] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][23] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][22] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][21] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][20] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][19] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][18] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][17] ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][47]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][46]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][45]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][44]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][43]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][42]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][41]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][40]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][39]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][38]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][37]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][36]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][35]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][34]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][33]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][32]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][31]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\this_r_reg[abh][30]__0 ) is unused and will be removed from module mult. WARNING: [Synth 8-3332] Sequential element (\u_aic/vstate_reg[1] ) is unused and will be removed from module cpu_core. WARNING: [Synth 8-3332] Sequential element (\u_aic/vstate_reg[0] ) is unused and will be removed from module cpu_core. WARNING: [Synth 8-3332] Sequential element (\u_aic/vcount_reg[20] ) is unused and will be removed from module cpu_core. WARNING: [Synth 8-3332] Sequential element (\u_aic/vcount_reg[19] ) is unused and will be removed from module cpu_core. WARNING: [Synth 8-3332] Sequential element (\u_aic/vcount_reg[18] ) is unused and will be removed from module cpu_core. WARNING: [Synth 8-3332] Sequential element (\u_aic/vcount_reg[17] ) is unused and will be removed from module cpu_core. WARNING: [Synth 8-3332] Sequential element (\u_aic/vcount_reg[16] ) is unused and will be removed from module cpu_core. WARNING: [Synth 8-3332] Sequential element (\u_aic/vcount_reg[15] ) is unused and will be removed from module cpu_core. WARNING: [Synth 8-3332] Sequential element (\u_aic/vcount_reg[14] ) is unused and will be removed from module cpu_core. WARNING: [Synth 8-3332] Sequential element (\u_aic/vcount_reg[13] ) is unused and will be removed from module cpu_core. WARNING: [Synth 8-3332] Sequential element (\u_aic/vcount_reg[12] ) is unused and will be removed from module cpu_core. WARNING: [Synth 8-3332] Sequential element (\u_aic/vcount_reg[11] ) is unused and will be removed from module cpu_core. WARNING: [Synth 8-3332] Sequential element (\u_aic/vcount_reg[10] ) is unused and will be removed from module cpu_core. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Start Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Area Optimization : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 633.441 ; gain = 455.750 --------------------------------------------------------------------------------- Finished Parallel Area Optimization : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 633.441 ; gain = 455.750 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Finished Parallel Synthesis Optimization : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 633.441 ; gain = 455.750 --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 633.441 ; gain = 455.750 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 674.555 ; gain = 496.863 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 674.555 ; gain = 496.863 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 674.555 ; gain = 496.863 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 674.555 ; gain = 496.863 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 674.555 ; gain = 496.863 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 674.555 ; gain = 496.863 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |BUFG | 1| |2 |CARRY4 | 97| |3 |DSP48E1 | 2| |4 |LUT1 | 192| |5 |LUT2 | 177| |6 |LUT3 | 539| |7 |LUT4 | 414| |8 |LUT5 | 751| |9 |LUT6 | 1384| |10 |MUXF7 | 17| |11 |RAM32M | 12| |12 |FDCE | 1044| |13 |FDPE | 46| |14 |FDRE | 164| |15 |IBUF | 195| |16 |OBUF | 410| +------+--------+------+ Report Instance Areas: +------+-----------------------------+-----------------------+------+ | |Instance |Module |Cells | +------+-----------------------------+-----------------------+------+ |1 |top | | 5445| |2 | u_aic |aic | 916| |3 | \get_irqs[0].iedge_inst |aic_edgedet | 7| |4 | \get_irqs[1].iedge_inst |aic_edgedet_0 | 7| |5 | \get_irqs[2].iedge_inst |aic_edgedet_1 | 7| |6 | \get_irqs[3].iedge_inst |aic_edgedet_2 | 7| |7 | \get_irqs[4].iedge_inst |aic_edgedet_3 | 7| |8 | \get_irqs[5].iedge_inst |aic_edgedet_4 | 7| |9 | \get_irqs[6].iedge_inst |aic_edgedet_5 | 9| |10 | \get_irqs[7].iedge_inst |aic_edgedet_6 | 144| |11 | u_cpu |cpu | 3922| |12 | u_datapath |datapath | 1859| |13 | u_regfile |register_file_two_bank | 523| |14 | u_decode |decode | 1346| |15 | core |decode_core | 330| |16 | u_mult |mult | 712| +------+-----------------------------+-----------------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 674.555 ; gain = 496.863 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 155 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 674.555 ; gain = 451.602 Synthesis Optimization Complete : Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 674.555 ; gain = 496.863 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 306 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 12 instances were transformed. RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 12 instances INFO: [Common 17-83] Releasing license: Synthesis 73 Infos, 101 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 680.992 ; gain = 462.383 report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.173 . Memory (MB): peak = 680.992 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Thu Jun 16 13:38:51 2016...