[J-core] Fwd: ISA manual for SH-2

[D. Jeff Dionne]

The JTAG debug on SuperH is implemented with (essentially) normal ISA instructions in a protected on chip 'ASE' memory block.  It is a debug stub speaking a proprietary protocol over JTAG, with hardware support on chip so that it can always trap into the stub.  This is flexible, but takes up a large amount of unproductive die area (in actual use).  A special jtag pod (E10A) is used, and the software requires Windows to run HUE (proprietary IDE).

J-Core takes a different approach.  The scan chain has a few bits (basically, IIRC, 56 bits total) to stop/step the CPU, insert an instruction into the fetch stage, and scan out the writeback bus.  total overhead is something like around 60-100 flops for the scan chain and capture regs, and a few dozen mux cells (assuming you had a TAP controller anyway).

So, unfortunately, we don't have any way to help with the (very different) SH implementation...

Cheers,
J.

> On May 28, 2017, at 04:59, <volkovdablo at gmail.com> <volkovdablo at gmail.com> wrote:
> 
> Btw, does anybody know anything about the SH4 debug stub that is necessary in the ROM to make the JTAG subsystem to work?.
> 
>  
> 
> I’m trying to hook a JTAG to my Dreamcast. So far everything is installed correctly, as the probe can detect the CPU. Unfortunately, the rom does not initialize the CPU id correctly, and the probe just says “Target not recognized SDSR = 0x12345678”.
> 
>  
> 
> I tried everything to find the location of this “SDSR” register, so I could initialize it to something during the boot rom. But there is no information whatsoever about this. Even Renesas refuses to answer me.
> 
>  
> 
> Anyone can bring some light to this?
> 
>  
> 
> Thanks in advance,
> 
> Javier.
> 
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