[J-core] Fwd: ISA manual for SH-2

[BGB]

On 5/26/2017 4:01 AM, D. Jeff Dionne wrote:
> On May 26, 2017, at 16:31, Francisco Javier Bizcocho Antúnez 
> <volkovdablo at gmail.com <mailto:volkovdablo at gmail.com>> wrote:
>
>> Hello all,
>> BGB could you describe a bit more which instructions from SH4 FPU 
>> were not used by C compiler?.
>
> I'm not sure what BGB's compiler does with the FPU, but basically 
> either GCC or libgcc.a / libm.a likely needs to have the option to use 
> basically all of the SH3 and later FPU instructions in order to 
> achieve the best possible floating point performance.   SH4 also has 
> some vector instructions, which are useful for things like signal 
> processing, which likely are not easy for a new compiler to use..
>

my comment was actually based on observations from GCC, not on my 
compiler (though, I can't say whether this also holds for math code in 
the C libraries).

as for which instructions I had seen going unused:
* FIPR, or basically the dot-product of two vectors.
* FTRV, which does a partial matrix multiply.
* FLDI0, FLDI1: which load float constants of 0.0 and 1.0
** I don't actually know why GCC doesn't use them (it seems to always 
load them from memory).
** my compiler may use them.
* FMAC: basically does a multiply-accumulate with floats.
** FRn=FRn+FR0*FRm
* FSCHG: inverts FPSCR.SZ
** GCC seems to pretty much never set SZ in my tests
*** though these tests were limited to SH4 in little-endian mode.

similarly, the XF and XD registers were not used by GCC in my tests 
(only FRn and DRn).

the FIPR, FTRV, and XF/XD registers were dropped from SH2A.
* the use of these registers also seems to be undefined in the C ABI.


in my FPU+SIMD extensions for my BJX1 extensions:
* XF/XD registers have been partially redubbed as FR16..FR31 and 
odd-numbered DRn registers.
* I made them freely usable by normal arithmetic instructions
** (though directly using FR16-FR31 requires use of 32-bit I-forms).
* they are also used in composing vectors.


>> Also I have another question related with the J2 cores. Do you guys 
>> think is possible to exchange the SH2 cores present in the Sega 
>> Saturn for to FPGAs with J2 cores on them?.
>
> Yes.
>

so they are pin-compatible? interesting.

>> This is due of the lack of JTAG capabilities of the original SH2 
>> cores, I want to test if I could use this configuration to develop 
>> some software that could run later on retail Sega Saturn machines.
>
> exchange in circuit is a bit hard, you likely want to emulate large 
> parts (basically building a functional equivalent) in FPGA.   There 
> was great interest in doing this by some of the original engineers 
> here in Japan, but the project never seems to have gotten off the 
> ground (building products for customers with J2 has been a priority).
>

makes sense.

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.j-core.org/pipermail/j-core/attachments/20170526/fa608756/attachment-0001.html>