[J-core] Using FST with VHDL?

[Rob Landley]

We've been been having a problem with the FST file format, as discussed
here:

  http://lists.j-core.org/pipermail/j-core/2017-March/000557.html

Which boils down to "nvc can write FST, but doesn't know how to
serialize complex data types used in VHDL, just verilog's booleans and
integers". We can extend nvc's fst.c to write out more data, but we
can't find a spec on what VHDL datatypes should look like in FST. Have
you addressed this before?

The j-core processor is an open source (BSD licensed) SOC implemented in
VHDL which makes extensive use of pretty much all of VHDL. It's a
clean-room chip compatible with the SuperH sh2 instruction set, boots
vanilla linux using a vanilla gcc toolchain and musl-libc. Our first
version, j2, is currently in feature freeze for first silicon.

We've been building it with xilinx tools for spartan 6 and kintex, and
using ghdl as the simulator. We'd like to switch to nvc+yosys for the
toolchain, and use nvc as the simulator too, but although we got it
simulating our chip to the point it runs the bootloader and self-test,
it can't write out waveforms that gtkwave can read...

Thanks,

Rob