[J-core] newbie

[D. Jeff Dionne]

On Aug 9, 2017, at 08:29, emanuel stiebler <emu at e-bbes.com> wrote:
> 
> Hi all,
> watched the video on yutube, from rob & jeff on the embedded linux conference, and thought it is pretty exciting. But, being new to j-core have some questions, and couldn't find the answers easily in the archives ...

Thanks.  We should put up some FAQs...

> a.) are the source now in GIT, somewhere on github?

We have not done a release in a while.  Not because we stopped, rather the opposite (customer deliverables).

> b.) I saw in the mailing lists, that it still uses Xilinx ISE, is anybody working on porting it to Vivado?

The RTL should work out of the box.  It is designed to be portable, and is developed in GHDL.  It is also tested with ASIC tool flows from time to time... Vivado is likely not blocked by porting issues.

The main thing stopping this is build infrastructure (Makefiles, scripts).   Using GUI builds (in the normal workflow) for something this big isn't something we contemplate.  There are then a few target process/FPGA specific things to deal with...  Pad ring I/O buffer instantiations, clock generators, etc.

> c.) Anybody is working on interfacing the memory to AXI? I know and understand, that it isn't free, but it can be used by both of the big guys (Altera and Xilinx) and would open the j-core to the newer FPGAs.

IP rights issues are the main reason we choose to do simple, straight forward bus structures.   AXI is interesting, but making sure there are no IP problems is a task we've not undertaken.  AMBA bridge is also interesting, and there is precedent that it likely has no practical problems (LEON and GR Lib) but we've not investigated that either.

We seek to be portable, so for instance we've not used any of the hard macro DDR controllers available on the Xilinx 7 series, nor anything that comes out of their CoreGen.  Since those are the types of things where AXI is used on FPGA and we avoided those to avoid relying on -any- vendor IP, it hasn't even come up yet.

Cheers
J

> Thanks!
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