[J-core] 2 CPU:s or nothing
daniel.viksporre at gmail.com
Fri Nov 25 15:36:06 EST 2016
2016-11-25 20:28 GMT+01:00, BGB <cr88192 at gmail.com>:
> On 11/25/2016 12:04 PM, Daniel V wrote:
>> Ok, some philosophical stuff here. And not critique of any kind.
>> I just want to remind about something...
>> If you want to boot a system you have a MCU and a CPU. Why cant both
>> be built upon j-core?
>> Is Linux capable of low latency stuff? Or do you use a FPGA for that?
>> So if you use a ASIC with j-core, do you then need 1ASIC, 1FPGA 1MCU?
>> Why is than that ASIC needed, and why is that FPGA needed? I
>> understand if you want to build a custom platform that you can dump
>> that FPGA and separate MCU, but it would be highly specific. But why
>> not make it more general?
>> Maybe that ASIC could have 1MCU and 1CPU. And why not let that MCU
>> have 2 memory blocks, A boot-loader, and a separate memory for loading
>> Arduino sketches or stuff like that. That MCU can then be used to
>> patch the holes that Linux has on the real-time side.
>> Maybe it's possible to reduce the need of the number of development
>> chains to a fewer number, by letting that MCU be built upon a J-core.
>> Maybe that wouldn't be space efficient, but is that really a concern.
>> It's a lot cheaper than to have a separate of the shelf MCU and board
>> space for it. If that MCU built upon J-core you could have a masked
>> boot ROM in the ASIC, and then be load new programs into RAM. That
>> wouldn't be efficient but cheep, and give fewer tool chains, and a lot
>> easier to design things with that ASIC later on.
>> Building a ASIC is a bit confusing. Because inefficient things is
>> cheep. I'm not promoting bad design. I'm promoting flexibility by
>> extending the thought a bit longer, and realize that extended
>> capability will save money and time later on and give a longer
>> usability of that ASIC, for other loads of projects by making it more
>> general. It would cost more for that first application. But is really
>> the ASIC the cost split over the number of pieces, than maybe that
>> separate MCU should be dumped.
>> I'm not saying that this is what to do, I'm saying that it's a thought
>> that may come in handy for building upon a possible future. It would
>> draw people to that platform, instead of away from it, because it does
>> not have any practical applications for them.
> something with both 1 or 2 CPU cores and an MCU could be nice.
> possibly, the MCU's address space and also IO peripherals are exposed as
> a memory-mapped IO device, then the CPU can send a program over to the
> MCU part and let it run, possibly with the MCU being entirely RAM,
> rather than the usual SRAM+Flash (idea being here that the CPU loads a
> program into it on startup).
Parallax Propeller has the different cores coupled to the same GPIO. I
don't remember exactly, but i think the I/O buffer from the different
cores goes to or gates and then to the output driver. So different
cores can read and write the same I/O pins.
// Daniel V.
More information about the J-core