[J-core] Adding J1 to the roadmap.

[Rob Landley]

During my recent trip to japan Jeff was kicking around the idea of
squeezing a smaller footprint j-core into the 8k ice40, not necessarily
for running Linux but instead aimed down at Arduino country.

The general idea was to yank the cache logic, prefetch, and multiplier
hardware out of j2, which gets the size down enough that it more or less
fits. If you're running out of sram (32k in ice40) you don't need cache
or prefetch, and the multiplier could be implemented using shifts and
adds (ala http://users.utcluj.ro/~baruch/book_ssce/SSCE-Shift-Mult.pdf)
in something like 33 clock cycles for the existing sh2 instruction, or
less for the smaller 16*16->32 muls.w instruction in the original superh
instruction set (hence "J1", which compilers already more or less know
how to target). Then you might have _just_ enough space left for one
uartlite instance.

The best part of this is we could _theoretically_ do it with a fully
open source toolchain, by gluing https://github.com/nickg/nvc to yosys.
(In practice this doesn't work yet, but Jeff put together the attached
tarball of stripped down source building a J1 prototype and sent it to
the nvc maintainer a couple weeks ago with a "ghdl does this, your thing
does this", and said maintainer has been fixing bugs as time allows ever
since.)

Once we've got the hardware working, it would be really nice to patch
the arduino gui to be able to build and load j1 code. And then we could
do a kickstarter for physical J1 chips, which could be TINY...

I'm not quite sure how to write this up for the roadmap yet, but I'm
working on it.

Rob
-------------- next part --------------
A non-text attachment was scrubbed...
Name: jcore-nvc-rtl-20160501.tar.gz
Type: application/gzip
Size: 99664 bytes
Desc: not available
URL: <http://lists.j-core.org/pipermail/j-core/attachments/20160518/16fdc26b/attachment-0001.bin>