[J-core] J-core ASIC, What tools should be used?

[D. Jeff Dionne]

There are 2 options:

You can use the usual commercial (Cadence, usually) flow.  The j-core RTL passes formal equivalence post P&R using the pure RTL test benches.  We use inferred (to flops) register files. Each CPU is about 0.4mm^2 using TSMC libraries and hits about 125MHz in 180nm, which is the process we (SEI) normally use, because we get really great analog performance, since we do mixed signal chips (plug: check out our -143dB noise floor, MHz bandwidth, Analog Front End chip, for instance).

You could use yosys for synthesis on a free flow, but you need a VHDL front end.  I have successfully linked it with Verific as the front end (but it is proprietary) and synthesised j-core.  There is some hope that NVC could be adapted, but right now it is a pure simulator.   For std cell libraries, look here http://vlsitechnology.org  Memory / Register File cells and compiler, we don't have... there have been some academic papers, but the implementations don't seem to be readily available.  For the rest of the tool flow, look here http://opencircuitdesign.com/qflow/  Doing a (pre-synthesised) hard macro of j-core that can reused is one of my goals.

We are working on plans for test chips, stay tuned.

Cheers,
J.

> On Aug 20, 2016, at 16:27, Daniel V <daniel.viksporre at gmail.com> wrote:
> 
> If you would like to look into making a custom CMOS design for j-core,
> is there any ideas on what tool-chain to use for that?
> 
> Maybe the design can be sized so that four layers can fit on a blank,
> for a multilayer mask(MLM). That is 4 layers on one mask, instead of
> paying for 4 masks.
> 
> But what type of process would it be preferable to design for? And
> what design rules should be used (do fabs provide that information
> without you sining a non disclosure agreement)?
> 
> // Daniel V.
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