[J-core] VHDL by Example

[Geoff Salmon]

On 08/16/2016 03:30 PM, Rob Landley wrote:
> On 08/16/2016 02:44 AM, Travis Ayres wrote:
>> What is the most complex code in the j-core system?
>>
>> I assume you have a package of types/records for system level items, and
>> assuming that's imported - where is it most tricky?

There's a number of packages. All (most?) are in files ending with 
"_pkg.vhd". For example, soc_top/components/cpu/cpu2j0_pkg.vhd contains 
the cpu component and record types for the cpu ports, and the 
cpu_instruction_o_t, cpu_instruction_i_t, cpu_data_o_t, and cpu_data_i_t 
records are used for the cpu's instruction and data buses. Anything 
connecting to the data bus uses this package so it can use these types.

Most tricky? Hmm, that's kind of subjective. I find the datapath process 
in soc_top/components/cpu/core/datapath.vhm quite complicated. It takes 
me a lot of time thinking and staring at simulation output to make a 
change there. soc_top/components/cpu/core/mult.vhm is mysterious unless 
you know exactly what the cpu's multiplier should be doing. I think the 
trickiness in these files comes from requiring a certain level of 
understanding how the cpu operates and not due to how we use VHDL though.

> My understanding is that at the design level, the tricky part is we use
> the "two process" VHDL design method.
>
>   http://ens.ewi.tudelft.nl/Education/courses/et4351/structured_vhdl.pdf
>
> This means we use VHDL compiler features that are in the standard, but
> not heavily used by other design strategies. For example we do as much
> late binding of signals as possible (instead of early binding), which in
> _theory_ gives the compiler more flexibility with layout and such, but
> in practice makes the optimizer do a lot more work.
>
> Given that, what parts of the code are most complex is a question for
> Geoff or Jeff. I'm still trying to learn the langauge. :)

I don't think anyone learning VHDL who wants to contribute should get 
hung up on the two process method or whatever "fancy" VHDL features we 
may be using. Even if VHDL features like record types or 
functions/procedures are less widely used, they're similar enough to 
features in almost every programming language. You can probably guess 
what they do from the name alone.

To grasp the two process style you should first understand:
- the difference between signal assignment and variable assignment
- what a VHDL processes does
- how to implement a register with a process. This is a signal whose 
value is set on a clock edge and can optionally be cleared with a reset 
signal.

With that base knowledge, the easiest way to understand how we use the 
two process method is to diff a vhm file and the corresponding vhd file. 
A perl script called v2p converts vhm files to vhd. You could write a 
vhdl file in the two process style directly if you wanted. v2p just cuts 
out some of the boilerplate.


If you're setting out to learn VHDL, it's essential you can simulate it 
and see the waveforms. I use GHDL [http://home.gna.org/ghdl/ 
https://github.com/tgingold/ghdl] to simulate and view the resulting 
waveforms in GTKWave [http://gtkwave.sourceforge.net/]. v0.33 of GHDL is 
available built for a number of platforms 
https://github.com/tgingold/ghdl/releases

I sent a tarball containing a couple vhdl entities and a script to 
simulate them to an older mailing list. I'll try to find that and post 
it here.

- Geoff