[J-core] Which lpddr?
D. Jeff Dionne
Jeff at SE-Instruments.com
Fri Apr 29 22:09:32 EDT 2016
J-Core DDR controller is set up for 16bit data bus, 14bit address.
The state machine can deal with DDR (1) or LPDDR (1), and is designed for a single (low cost, commodity) chip. All our current generation hardware uses 1.8v LPDDR in 60 BGA. These are available from 512Mbit to 2Gbit, from various vendors, for cheap. We have boards that run DDR (non LP) but these have not been tested recently.
The RTL could support DDR2 or LPDDR2 with a small change to the state machine. It would be a larger change to expand the bus from 16bits. Remembering that Double Data Rate means 16*2=32bits per clock cycle, even 16bit DDR1 is therefore memory bandwidth of about:
Assuming 70% throughput, which is realistic given refresh, precharge, the ram's internal pipeline... The FPGA implementation is clocking about 1/2 as fast as this. Even this 1/2 bandwidth implementation is no where near a system bottleneck. Even a 1024x768 24bit video frame buffer would only use 142Mbyte/sec, or about 1/2 of the FPGA implementation's memory bandwidth.
The DMA (not released yet) and cache controllers try to make best use of the memory bandwidth by bursting where possible. LPDDR has longer bursts than DDR, but I'm not sure if that matters to the implementation.
> On Apr 30, 2016, at 10:32, Rob Landley <rob at landley.net> wrote:
> According to wikipedia there are 4 lpddr specs:
> It looks like we're using lpddr2, because of the 2 gigabit max?
> Samsung says it has has 4 gigabit lpddr3 and 8 gigiabit lpddr4:
> So in theory we're not _that_ far off from being able to do a gigabyte
> of ram. Modulo expanding the cache tags and finding chips that are
> reasonably priced and don't require our chip to run at 800mhz to talk to
> them. :)
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