[J-core] Second J-core source release available (really, this time)

[Rich Felker]

Our release issues have been worked out and the second release
(20160418) of the J-core source is now available on j-core.org.
Highlights compared to the previous release include:

- Addition of dcache and icache and a new DDR controller, drastically
  improving performance.

- The CAS.L instruction (an addition to the SH-2 ISA for atomic
  compare and swap) now works.

- Boot loader now loads a device tree blob (DTB) from the SD card to
  pass to the kernel it loaded, for use with new device tree based
  kernels. (Once device tree bindings are stabilized and made
  official, the DTB will be moved into the boot ROM.)

- Dual-core SMP support at the source level (however, this needs a
  board with a bigger FPGA, and a corresponding target/boards file, in
  order to use it on actual hardware).

- ...and probably lots of other things I missed.

An updated prebuilt bitstream for the Numato Mimas v2 board (the only
board with support included in the release) is also provided.

Updated kernel images and userspace are not up yet simply because I
don't have documentation on how to reproduce them from source. I'll
post to the list when they're ready. In the mean time, the old vmlinux
image works on the new bitstream, but lacks any new features.

Rich